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flexiFLASH Architecture


The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device programming and configuration. The Figure below provides an overview of the arrangement of Flash and SRAM configuration cells within the device.

flexiFLASH Architecture

flexiFLASH Benefits

Instant-on

At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration cells that control the operation of the device. This is done with massively parallel buses enabling the parts to operate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On.

LatticeXP2 Instant-On

Single Chip

The on-chip Flash enables a single-chip solution eliminating the need for external boot memory and thereby reducing the solution footprint. The single die allows smaller packages to be used than currently have been delivered using hybrid stacked die approaches.

Single Chip - small footprint

~3K LUT Hybrid Non-volatile Device and 5K LUT True Non-volatile Device

FlashBAK BlockRAM

The FlashBAK capability of the parts enables the contents of the EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the device configuration.

FlashBAK Technology

Serial TAG Memory

Serial memory is available to allow the storage of small amounts of data such as calibration coefficients and error codes.

Serial Tag Memory
Device TAG Memory (Bits)
XP2-5 632
XP2-8 768
XP2-17 2186
XP2-30 2640
XP2-40 3384
 

 

Design Security

For applications where security is important, the lack of an external bit stream provides a solution that is inherently more secure than SRAM only FPGAs.  Three features further enhance the inherent security of this solution:

    • Control bits that once set prevent the Flash and SRAM areas from being read 
    • An optional 64-bit Flash lock key that is required for erasure and programming prevents accidental or unauthorized reprogramming 
    • An optional One Time Programmable (OTP) mode that blocks any future erasure or reprogramming provides the ultimate assurance that the FPGA contents have not been tampered with.

Design Security