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Most FPGA solutions in the market are SRAM based, at power-up they are blank and do not perform user functions. The SRAM cells of these FPGAs have to be loaded with configuration data based on user functions from external boot memories. This download of configuration data from boot memories can take many tens or hundreds of milliseconds. Non-volatile FPGA solutions store configuration data on-chip eliminating the need for external boot memory and associated long configuration times. One approach to providing non-volatility has been to use anti-fuse technology, although these FPGAs are non-volatile they cannot be reconfigured: each time a user function is changed a new FPGA device has to be programmed. The LatticeXP FPGA family is non-volatile and reconfigurable. LatticeXP FPGA Configuration MemoriesThe LatticeXP FPGA family combines SRAM and FLASH configuration memories in the same device. The SRAM memory cells control the logic operation of the LatticeXP FPGA devices, and the FLASH memory cells store the configuration data. There is a wide data-path connecting the two memories. At power-up the SRAM bits are loaded from the on-chip FLASH memory via this wide bus resulting in logic availability in less than 1ms after power good. In addition, during device operation (user mode), the SRAM memory may be reconfigured from the FLASH memory by toggling a pin or by issuing the correct commands through the device configuration ports. Figure 1 shows the operation of the different memories within the LatticeXP FPGA devices. Both the FLASH memory and the SRAM memory can be reprogrammed/reconfigured via either a JTAG port or a sysCONFIG port (microprocessor style interface).  Figure 1 - Configuration Memories in the LatticeXP
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On-chip non-volatile memory allows the LatticeXP FPGA devices to be ready for operation within one millisecond of power good. This approach contrasts with SRAM based FPGA devices that typically require tens or hundreds of milliseconds for configuration. The rapid logic availability of non-volatile FPGAs reduces complexity in system design and is a desirable characteristic in many common applications, including: Power-up Control, Control Logic and Bus Bridging/Interface.
Today FPGAs are located in the heart of the system, replacing functions traditionally performed by ASICs and Microprocessors. With current FPGA technology gate counts running into the millions, FPGAs are an attractive target for piracy. FPGA designers are increasingly concerned about issues of cloning, reverse engineering, overbuilding and theft of service. The SRAM FPGAs most commonly used by system designers need to be configured from a boot device every time the system powers up. This link between the boot device and the FPGA represents a significant security risk. The configuration data is exposed and vulnerable to piracy while the system powers up. The LatticeXP FPGA devices, which have a security scheme that prevents read back if desired, eliminates this security risk.
Traditional SRAM FPGAs require a boot memory to load the SRAM configuration at power-up. Sometimes configuration loading is done via the on-board microprocessor or in other applications a stand-alone boot memory is utilized. Neither solution is ideal. Booting from the system microprocessor introduces additional interdependencies between hardware and software development. It also requires that the microprocessor be up and running prior to the configuration of the FPGAs, precluding their use for system heartbeat functions. Using a stand-alone boot memory increases the board area footprint of the solution and the bill of materials (BOM) along with the associated costs. By integrating the boot memory on-chip, the LatticeXP FPGA provides an alternative, more elegant solution.
LatticeXP FPGA devices have flexible reprogramming / re-configuration modes. Even when the LatticeXP FPGA device is operational, the internal configuration FLASH memory can be reprogrammed in the background via 1149.1 port. When desired the SRAM configuration memory can be reconfigured on the fly (<1 mS) from the FLASH memory by toggling a pin or issuing the correct commands through the device configuration ports. In addition, the internal configuration SRAM can also be reprogrammed from sysCONFIG parallel port within tens of milliseconds.