System Level Support

System Bus

Each LatticeSC device connects the FPGA elements together with a standardized bus framework referred to as system bus. Implemented using the open standard, on chip AMBA AHB2.0 specification bus, the system bus facilitates communication between the Micro Processor Interface (MPI), configuration logic, user logic and Serial Memory Interface (SMI). AHB provides a high-performance bus that aligns with current synthesis design flows. Multiple bus masters optimize system performance by sharing resources between different bus masters such as the MPI and configuration logic. The wide data bus configuration of 32-bits with 4-bit parity supports high-bandwidth, data-intensive applications. AMBA enhances design reuse by defining a common backbone for IP modules.

Microprocessor Interface (MPI)

The LatticeSC family devices have a dedicated synchronous MPI function block. The MPI is programmable to operate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for configuration and read-back of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. In addition to dedicated-function registers, the MPI bridges to the AMBA compliant system bus through which the PowerPC bus master can access the FPGA configuration logic, EBR and other user logic. There is also capability to interrupt the host processor either by a hard interrupt or by having the host processor poll the MPI and the embedded system bus.

Boundary Scan Testability

All LatticeSC devices have boundary scan cells that are accessed through an IEEE 1149.1 and IEEE 1532 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification.