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Serializer-DeSerializer
LatticeSC devices feature up to 32 channels of embedded SERDES with the industry's most versatile Physical Coding Sublayer (PCS) block called flexiPCS. The SERDES and flexiPCS blocks can be configured to support numerous industry standard high-speed data transfer protocols.
Each SERDES channel contains dedicated transmit and receive circuitry for high-speed full-duplex serial data transfers at data rates up to 3.8 Gbps. The flexiPCS logic can be configured to support an array of popular data and TDM protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10 Gbps or above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X specification), 10GbE (XAUI) 1.02 or 2.04 Gbps Fibre Channel, PCI-Express, and Serial RapidIO. In addition, the protocol based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface.
The PCS also provides bypass modes that allow a direct 8 or 10-bit interface from the SERDES to the FPGA logic. Each SERDES pin can also be independently DC coupled and support both high-speed and low-speed operation on the same SERDES pin which is required by some Serial Digital Video applications.
LatticeSC SERDES Features & Benefits
- Up to 32 Channels of High-Speed SERDES
- 600 Mbps to 3.8 Gbps per channel
- High RX Jitter Tolerance (0.8UI at 3.125G)
- Low TX jitter (0.25 UI at 3.125G)
- Low Power (100 mW per channel typical)
- SERDES Only mode allows direct 8- or 10-bit interface to FPGA logic
- Out-of-band signal interface allows same pin operation down to DC rates
- flexiPCS: Feature Rich Embedded Physical Coding Sublayer (PCS)
- Up to 32 Channels of full-duplex data supported per device
- Multiple protocol support on one chip
- Support for Popular Packet Based Standards
- Support for generic 8b/10b encoding/decoding
- Support for SONET
- PCI Express
- PCI Express data scrambling and descrambling (Both D1.0 and D1.0a polynomials)
- Multi-channel alignment for support of x1 to x32 PCI-Express
- Receiver Detection
- Gigabit Ethernet
- Single channel provides 1G Ethernet link to GMII compliant FPGA logic interface
- IEEE 1000BASE-X compliant
- 8b10b encoding/decoding
- Access Clause 22 PHY registers in Auto-negotiation mode
- Comma character word alignment
- Clock Tolerance Compensation circuit
- CRC generation/checking
- 10Gb Ethernet
- Single Quad (4 channel) support of XAUI interface specification at FPGA logic interface
- 10GbE /A/K/R/ idle insertion and removal
- 10GbE synchronization state machine controls comma alignment
- 10GbE XAUI deskew state machine controls multi-channel alignment and monitors alignment status
- Clock Tolerance Compensation logic performs idle insertion and removal
- Fibre Channel
- Fibre Channel link state machine to report link status
- Fibre Channel EOF ordered set conversion to correct disparity
- 1.02/2.04 Gbps Fibre Channel support on single channel and 10G Fibre Channel support on one quad (4 channels)
- Independent selection of 1.02 or 2.04 Gbps for each transmit channel and receive channel
- Serial RapidIO
- Random /A/K/R/ insertion in transmit path and idle replacement in receive path
- Multi-channel alignment for support of 1x to 32x RapidIO
- SONET Based Functionality
- STS-48 and STS-12 Framers
- Supports any length of concatenation within an STS-12/STS-12c or STS-48/STS-48c frame
- Auto-TOH insertion of A1, A2, and Section B1 bytes into transmitted data frames
- SONET compliant scrambling and descrambling
- B1 checking, AIS insertion/checking and RDI-L insertion and checking
- STS-48/STS-12 pointer interpreter function with STS-1 granularity
- TFI-5 Link Layer support
- Multiple Protocol Compliant Multi-Channel Aligner
- Provides twin channel, quad and multi-quad alignment receive data alignment
- Allows alignment of data between two SC devices (up to 64 channels total)
- Clock Domain Handling for Smooth Clocking Hand off Between Line and FPGA Logic
- Ability to gear data by 2:1 into the FPGA core
- Multiple transmit and receive clock connections available to FPGA logic on both primary and secondary clock lines
- Loopback Modes for Improved System Debugging and Testability
- Far End Loopback (Receive to Transmit) provided for testing line connections to and from SC device
- Near End Loopback (Transmit to Receive) provided to test connections across PCS/FPGA logic interface
- Integrated 27 and 231 PRBS generator/checkers for use in generating randomized data patterns for loopback testing
- Error insertion and interrupt capability
READ MORE: How the Lattice SC SERDES and flexiPCS enable packet based serial transmission
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