PURESPEED I/O Technology

Overview

The LatticeSC FPGAs feature PURESPEED I/O technology, combining powerful buffers with dedicated I/O Logic to provide seamless and robust parallel source synchronous I/O solutions. The resulting solution packs a powerful punch providing support for an industry-best 2Gbps throughput per differential I/O pair. PURESPEED I/O technology consists of:

I/O Register Blocks

Dedicated shift register and Mux/Demux circuitry DDR and SDR is included to provide seamless, PVT compensated transitions from the high speed I/O to FPGA fabric clock domains. This works in conjunction with dedicated clock dividers that perform by-2 and by-4 clock divisions without using any PLL resources on the FPGA fabric.

INDEL Block with Adaptive Input Logic (AIL)

The 144 tap INDEL block is used to adjust the delay in the data path on a signal-by-signal basis to ensure that it has sufficient set-up and hold time margins as defined by the user. For per-bit automatic monitoring and dynamic control the Adaptive Input Logic (AIL) block ensures that the user-defined margins are adhered with changes in Process, Voltage and Temperature (PVT). This capability simplifies the system level design of high-speed interfaces and ultimately allows higher overall speeds to be achieved compensated over PVT.

The INDEL block can also be directly controlled by the DLL for bus-based alignment.

PURESPEED I/O Buffer

Programmable I/O buffers are arranged around the periphery of the device in seven groups referred to as Banks. The PURESPEED I/O buffers allow users to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. The availability of programmable on-die termination for both input and output use, further enhances the utility of these buffers.

Supported I/O Standards

The LatticeSC sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 12, 15, 18, 25 and 33 standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, termination resistance, bus maintenance (weak pull-up, weak pull-down, PCI clamp or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL, HSTL, GTL (input only), GTL+ (input only), PCI33, PCIX33, PCIX15, AGP-1X33 and AGP2X33. Differential standards supported include LVDS, RSDS, BLVDS, MLVDS, LVPECL, HyperTransport, differential SSTL and differential HSTL. The table below shows the I/O standards (together with their supply and reference voltages) supported by the LatticeSC devices.

Programmable On-Die Termination (ODT)

Many of the I/O standards supported by the LatticeSC devices require termination at the transmitter, receiver or both. The SC devices provide the capability to implement many kinds of termination on-chip, minimizing stub lengths and hence improving performance. Utilizing this feature also has the benefit of reducing the number of discrete components required on the circuit board. Support for the following is included:

• SINGLE ENDED INPUTS: Serial, Parallel and Thevenin
• SINGLE ENDED OUTPUTS: Parallel and Thevenin.
• NEW LOW POWER SINGLE ENDED OUTPUT: Termination to Vtt for 60-70% less power than Thevenin Equivalents!!
• NEW DDR2 Switchable Termination: Autmatic on/off switching depending on read/write cycles
• NEW DIFFERENTIAL INPUTS with internal CTAP to filter common mode noise.

Hot Socketing

The LatticeSC devices have been carefully designed to ensure predictable signal pad behavior during power-up and powerdown. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits, this allows for easy integration with the rest of the system. These capabilities make the LatticeSC ideal for many multiple power supply and hot-swap applications.

Supported Source Synchronous Interfaces

The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify the implementation of Source Synchronous interfaces. The table below lists Source Synchronous and DDR/QDR standards supported in the LatticeSC.