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System Packet Interface, Level 4, Phase 2 (SPI4.2) is Optical Internetworking Forum's (OIF) recommended interface for the interconnection of Physical Layer (PHY) devices to Link Layer devices for 10 Gb/s aggregate bandwidth applications. SPI-4 is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications.
SPI-4 has the following general characteristics:
- Point-to-point connection (i.e., between single PHY and single Link Layer device)
- Support for 256 ports (suitable for STS-1 granularity in SONET/SDH applications (192 ports) and Fast Ethernet granularity in Ethernet applications (100 ports))
- Transmit/Receive Data Path is 16 bits wide
- Contains In-band port address, start/end-of-packet indication, error-control code
- Minimum data rate of 622 Mb/s per line. Source-synchronous double-edge clocking, 311 MHz minimum
- Transmit/Receive FIFO Status Interface implemented using LVTTL I/O or optional LVDS I/O
- Maximum 1/4 data path clock rate for LVTTL I/O, data path clock rate (double-edge clocking) for LVDS I/O
- 2-bit parallel FIFO status indication
- In-band Start-of-FIFO Status signal
- Source-synchronous clocking.
Data is transferred in bursts that have a provisionable maximum length, with the exception of transfers that terminate with an EOP. Information associated with each transfer (port address, start/end-of-packet indication and error-control coding) is sent in 16-bit control words.
LatticeSCM SPI4.2 Core Features:
- Fully compliant with OIF-SPI4-02.0 Specification
- Up to Two independent SPI4.2 Cores embedded in the LatticeSCM family of devices
- Up to 256 logical ports supported
- Transmit/Receive Data Path
- 16 bits wide, in-band port address, SOP, EOP indication, error controlo
- LVDS I/O (IEEE 1596.3 – 1966, ANSI/TIA/EIA-644-1995)
- Source synchronous double edge clocking at 311MHz minimum
- Static and Dynamic Alignment Modes
- Up to 1 Gbps Dynamic Phase Alignment using the AIL logic in the SC IOs
- Up to 700 MHz Static Alignment
- Additional Quarter Rate Mode for sub 10G traffic
- Transmit/Receive FIFO Status
- 2 bit parallel FIFO status indication, in-band Start of FIFO status
- LVTTL I/O or optional LVDS I/O (IEEE 1596.3)
- Source synchronous clocking
- Programmable burst modes to support NPU requirements
- Pre-engineered hard cores using MACO technology to conserve power, FPGA resources and designer time.
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