Low-speed CDR Support

The low-speed CDR block diagram

The LatticeSC LSCDR (low-speed clock and data recovery) MACO core is a fully integrated low-power clock and data recovery (CDR) block designed for low-speed serial communication systems. The clock and data recovery circuit (CDR) is a digital base band circuit that post processes a demodulated binary signal to produce an optimally sampled data bit stream and clock signal that is synchronized with the incoming data. It extracts timing information and data from serial input data rates between 100 to 500Mbps. Its design eliminates sensitive noise entry points of clock forwarded schemes thus making it less susceptible to board-level interaction and helping to ensure optimal jitter performance.

The highlights of the low-speed CDR MACO are:

• Capable of retiming data streams with rates ranging from 100 Mbps to 500 Mbps.
• Can accommodate jitter components up to 0.85UI.
• No additional logic required (FIFOs built-in).
• Can handle maximum 18 channels of data.
• Available in LFSCM40, LFSCM80, and LFSCM115.
• A synchronous mode is included for parallel interfaces- this mode provides additional 36-bit AIL-like channels.
• Supports pathological signals.
• Connects to the SERDES bypass signal that enables multi-rate support on a single pin.

• LatticeSC MACO Core LSCDR1X18 Low-Speed Clock and Data Recovery User's Guide