LatticeSCM Ethernet/flexiMAC Support

Ethernet is a large and diverse family of frame-based computer networking technologies for local area networks (LANs). This standard defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/data link layer, and a common addressing format. LatticeSC provides a flexible packet framer and parser that can implement Layer 2 (Data Link Layer or MAC) functionality for various standards. Implemented in MACO technology, the FlexiMAC functionality complements the LatticeSC SERDES and the Layer 1 (Physical Layer) multi-protocol functionality of the Physical Coding Sublayer (PCS). This results in a complete Layer 1/Layer 2 solution for 1G/10G Ethernet standards and provides customers with integrated 1GE/10GE solutions without using up valuable FPGA gates.

The highlights of the Ethernet support in LatticeSC are:

• Only FPGA-based SERDES to include full 10 GE and 1 GE PCS embedded
• Only FPGA to include full-featured 1 GE and 10 GE MACs embedded on-chip, implemented using ASIC technology
• Only FPGA that provides complete Layer 1/Layer 2 support on-chip for 1GE/10GE applications without using any FPGA resources
• Reliable, high-speed, low-power, fully verified Ethernet functionality
• No licensing fees involved, fully verified functionality: more reliable than soft FPGA implementations
• Evaluation boards available to demonstrate operation of MAC

flexiPCS: Packet Protocols

flexiMAC Multi-Protocol Support

The highlights of flexiMAC are:

• Ethernet
  
  • flexiMAC is a flexible packet framer and parser that can implement Layer 2 (Data Link Layer or MAC) functionality for various standards
  • The flexiMAC functionality complements the LatticeSC SERDES and the Layer 1 (Physical Layer) multi-protocol functionality of the Physical Coding Sublayer (PCS)
  • This yields a complete Layer 1/Layer 2 solution for 1G/10G Ethernet standards
  • Provides customers with integrated 1GE/10GE solutions without using up valuable FPGA gates
• PCI Express
  
  • Implements PCI Express PHY and Data Link Framing
  • DLLP generation of Acks/Nacks
  • CRC (CRC16 & CRC32) Generation and Checking for DLPs and TLPs
  • Flow control Packets (FC1/2) Initialization
  • Enforcement of flow control rules
  • Together with the LTSSM MACO, provides customers with a highly integrated PCI Express x1 and x4 solution without using up valuable FPGA gates.

The flexiMAC block diagram