MACO: On-Chip Structured ASIC Blocks

The LatticeSCM family combines the flexibility of a programmable architecture with embedded ASIC blocks implementing a variety of high-density, high-speed functions.The layout of the LatticeSC FPGA is a regular and homogeneous array of programmable logic cells (PFUs) surrounded by programmable I/O cells (PICs). At the top of the device is located embedded SERDES channels which connect to embedded multi-purpose physical coding sub-layer (PCS) blocks for managing high-speed serial data transfers. The PCS block can be bypassed to transfer serial data directly to the FPGA fabric. Rows of embedded block RAM (EBR) are “striped” across the array for efficient connectivity to the PFUs. Special configurable interconnect blocks (CIB) contain dedicated resources for routing signals to/from the block RAM. At the end of each EBR row (see figure below) is an area of silicon that Lattice has made available for a “structured ASIC” block, allowing us to embed pre-engineered, high perfomance IP using a fraction of the area and power of an equivalent FPGA based implementation. We call this concept the Masked Array for Cost Optimization (MACO).

The LatticeSCM family provides designers access to these embedded IP blocks, and when combined with a state-of-the-art FPGA array and world-class SERDES technology, they offer the most flexible and high-performance programmable platform available today.

At the heart of the MACO block is a sea of 50,000 ASIC gates. A library of cells was created with Fuijtsu’s CS100A 90nm CMOS process technology and optimized for speed, power dissipation, and area.

Advantages of MACO

MACO provides the customer multiple advantages: speed, density, and lower power dissipation.

Improved performance vs. FPGA gates: MACO dramatically improves design performance. Since MACO is a 90nm cell-based technology like a structured ASIC, it is capable of > 700MHz performance with little design effort. Ample connectivity is provided to connect each MACO to LatticeSC I/O technology, as well as embedded RAM and programmable FPGA fabric.
Increased Device Density: MACO conserves area by shrinking 5,000 equivalent LUTs into a much smaller silicon area (approximately 10x). With multiple MACO blocks per device, this significantly boosts device density. Since MACO is ideal for industry-standard IP cores, this means that valuable LUT-based silicon is reserved for value-added design features.
Reduced Power Dissipation: MACO conserves power by implementing IP previously targeted for LUT-based architectures in 90nm cell-based technology. MACO blocks will not exceed 200mW per site, even at 700MHz performance. This type of power dissipation cannot be matched in 90nm LUT architectures running at similar clock rates. Typically a design implemented in MACO would consume 1/2 the power relative to an equivalent FPGA design.

LatticeSCM Family

By enabling the MACO blocks on each LatticeSC device, the LatticeSCM devices will offer pre-engineered IP based on industry-standard interfaces. Included on the LatticeSCM devices will be memory controllers, SPI4.2 interfaces, multiprotocol MAC, low-speed CDR, and PCI Express Link Training and Status State Machine blocks. The figure on the right illustrates the MACO block layout for the LatticeSC family.

A table of available pre-engineered IP available on MACO enabled LatticeSCM devices is shown below:

Embedded Memory Controllers

High-bandwidth FPGA system-on-chip designs commonly interface to off-chip SDRAM and SRAM memories for large packet buffering. The LatticeSCM devices provide pre-engineered high speed memory controllers using MACO technology that support the major high-speed memory standards implemented in many communications systems: DDR I/II SDRAM and QDR I/II SRAM. Read more

SPI4.2 Core

System Packet Interface, Level 4, Phase 2 (SPI4.2) is Optical Internetworking Forum's (OIF) recommended interface for the interconnection of Physical Layer (PHY) devices to Link Layer devices for 10 Gb/s aggregate bandwidth applications. The LatticeSCM devices provide pre-engineered SPI4.2 cores using MACO technology providing customers with the industry's highest-performance and lowest power SPI4.2 implementation. Read more

PCI Express Solution

The LatticeSCM PCI Express solution is the industry’s first embedded ASIC-based programmable PCI Express solution. Lattice provides customers with the smallest and lowest power FPGA based implementation for a complete x4 PCI Express Endpoint. Read more

Ethernet Support

LatticeSC provides a flexible packet framer and parser that can implement Layer 2 (Data Link Layer or MAC) functionality for various standards. Implemented in MACO technology, the FlexiMAC functionality complements the LatticeSC SERDES and the Layer 1 (Physical Layer) multi-protocol functionality of the Physical Coding Sublayer (PCS). Read more

Low-speed CDR Support

The LatticeSCM LSCDR (Low-speed Clock and Data Recovery) MACO core is a fully integrated low-power Clock and Data Recovery (CDR) block designed for low-speed serial communication systems. The clock and data recovery circuit (CDR) is a digital base band circuit that post processes a demodulated binary signal to produce an optimally sampled data bit stream and clock signal that is synchronized with the incoming data. Read more