The LatticeSCM family combines the flexibility of a programmable architecture with embedded ASIC blocks implementing a variety of high-density, high-speed functions.The layout of the LatticeSC FPGA is a regular and homogeneous array of programmable logic cells (PFUs) surrounded by programmable I/O cells (PICs). At the top of the device is located embedded SERDES channels which connect to embedded multi-purpose physical coding sub-layer (PCS) blocks for managing high-speed serial data transfers. The PCS block can be bypassed to transfer serial data directly to the FPGA fabric. Rows of embedded block RAM (EBR) are “striped” across the array for efficient connectivity to the PFUs. Special configurable interconnect blocks (CIB) contain dedicated resources for routing signals to/from the block RAM. At the end of each EBR row (see figure below) is an area of silicon that Lattice has made available for a “structured ASIC” block, allowing us to embed pre-engineered, high perfomance IP using a fraction of the area and power of an equivalent FPGA based implementation. We call this concept the Masked Array for Cost Optimization (MACO).
The LatticeSCM family provides designers access to these embedded IP blocks, and when combined with a state-of-the-art FPGA array and world-class SERDES technology, they offer the most flexible and high-performance programmable platform available today.
At the heart of the MACO block is a sea of 50,000 ASIC gates. A library of cells was created with Fuijtsu’s CS100A 90nm CMOS process technology and optimized for speed, power dissipation, and area.
MACO provides the customer multiple advantages: speed, density, and lower power dissipation.
By enabling the MACO blocks on each LatticeSC device, the LatticeSCM devices will offer pre-engineered IP based on industry-standard interfaces. Included on the LatticeSCM devices will be memory controllers, SPI4.2 interfaces, multiprotocol MAC, low-speed CDR, and PCI Express Link Training and Status State Machine blocks. The figure on the right illustrates the MACO block layout for the LatticeSC family.
A table of available pre-engineered IP available on MACO enabled LatticeSCM devices is shown below:
| Device | SCM15 | SCM25 | SCM40 | SCM80 | SCM115 |
|---|---|---|---|---|---|
| 1 | 2 | 2 | 2 | 4 | |
| SPI4.2 Blocks | 1 | 2 | 2 | 2 | 2 |
| Memory Controller Blocks: DDR1 DRAM Mode DDR2 DRAM Mode QDR2 SRAM Mode |
1 | 2 | 2 | 2 | 2 |
| Low-speed CDR | 0 | 0 | 2 | 2 | 2 |
| PCI Express LTSSM (PHY) | 1 | 0 | 2 | 2 | 2 |
High-bandwidth FPGA system-on-chip designs commonly interface to off-chip SDRAM and SRAM memories for large packet buffering. The LatticeSCM devices provide pre-engineered high speed memory controllers using MACO technology that support the major high-speed memory standards implemented in many communications systems: DDR I/II SDRAM and QDR I/II SRAM. Read more
System Packet Interface, Level 4, Phase 2 (SPI4.2) is Optical Internetworking Forum's (OIF) recommended interface for the interconnection of Physical Layer (PHY) devices to Link Layer devices for 10 Gb/s aggregate bandwidth applications. The LatticeSCM devices provide pre-engineered SPI4.2 cores using MACO technology providing customers with the industry's highest-performance and lowest power SPI4.2 implementation. Read more
The LatticeSCM PCI Express solution is the industry’s first embedded ASIC-based programmable PCI Express solution. Lattice provides customers with the smallest and lowest power FPGA based implementation for a complete x4 PCI Express Endpoint. Read more
LatticeSC provides a flexible packet framer and parser that can implement Layer 2 (Data Link Layer or MAC) functionality for various standards. Implemented in MACO technology, the FlexiMAC functionality complements the LatticeSC SERDES and the Layer 1 (Physical Layer) multi-protocol functionality of the Physical Coding Sublayer (PCS). Read more
The LatticeSCM LSCDR (Low-speed Clock and Data Recovery) MACO core is a fully integrated low-power Clock and Data Recovery (CDR) block designed for low-speed serial communication systems. The clock and data recovery circuit (CDR) is a digital base band circuit that post processes a demodulated binary signal to produce an optimally sampled data bit stream and clock signal that is synchronized with the incoming data. Read more
© Lattice Semiconductor Corporation 2012
