Extreme Performance FPGA Fabric

Programmable Function Unit (PFU)

The core of the LatticeSC devices consists of PFU blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in the figure below. All the interconnections to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.

PFU Slice

Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to implement 5, 6, 7 and 8 Input LUTs (LUT5, LUT6, LUT7 and LUT8). There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions.

LatticeSC PFU Benchmark Performance

The table below shows several wide logic blocks that were used to benchmark the LatticeSC PFU.

1. For additional information, see Typical Building Block Function Performance table in this data sheet.
2. Advance information (-7 speed grade).