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Embedded Block RAM (EBR)
Each EBR block can implement single port, true dual port, pseudo dual port or FIFO memories. Dedicated FIFO support logic allows the LatticeSC devices to efficiently implement FIFOs without consuming LUTs or routing resources for flag generation. Each block can be used in a variety of depths and widths as shown in the table below. Memory with ranges from x1 to x18 in all modes: single port, pseudo-dual port and FIFO also providing x36.
LatticeSC FPGA Memory Sizes
| Memory Mode |
Configurations |
| Single Port |
16,384 x 1 |
2,048 x 9 |
| 8,192 x 2 |
1,024 x 18 |
| 4,096 x 4 |
512 x 36 |
| True Dual Port |
16,384 x 1 |
2,048 x 9 |
| 8,192 x 2 |
1,024 x 18 |
| 4,096 x 4 |
|
| Pseudo Dual Port |
16,384 x 1 |
2,048 x 9 |
| 8,192 x 2 |
1,024 x 18 |
| 4,096 x 4 |
512 x 36 |
| FIFO |
16,384 x 1 |
2,048 x 9 |
| 8,192 x 2 |
1024 x 18 |
| 4,096 x 4 |
512 x 36 |
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