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Clock Management: Analog PLLs and Advanced DLLs

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The LatticeSC provides a no-compromise clock management solution by featuring both PLLs and DLLs in the device. This enables the designer to utilize excellent frequency synthesis and clock output capabilities of a PLL and the superior incoming clock management capabilities of a DLL.

Analog PLLs

PLLs are ideal for applications requiring the lowest out put jitter or jitter filtering. The LatticeSC PLLs provide the following capabilities:

  • Ability to synthesize clock frequencies and drive signals off chip
  • Highly granular multiply and divide capabilities
  • Clock injection removal
  • Clock phase adjustment
  • Clock skew control
  • Spread Spectrum support

LatticeSC PLL Features:

  • Output 1.56 MHz to 1 GHz
  • VCO 100 MHz to 1 GHz
  • Input 15 MHz to 1 GHz
  • Low output jitter
  • Dynamic reconfiguration of loop parameters
  • Programmable M and N dividers (1x–64x)
  • 100ps typical programmable phase delay
  • Spread Spectrum generation support (1, 2 or 3%)
  • 8 per device

PLL Block Diagram

LatticeSC sysCLOCK PLL Block Diagram

LatticeSC Advanced DLLs

DLLs assist in the management of clocks and strobes. DLLs are well suited to applications where the clock may be stopped or transferring jitter from input output is important, for example forward clocked interfaces.

The user can configure the DLL for many common functions such as:

  • Clock injection match
  • Clock injection delay removal
  • Duty cycle correction
  • Time reference delay

DLL Features:

  • Output 1.56 MHz to 700 MHz
  • Input 100 MHz to 700 MHz
  • Output dividers (1/2, 1/4)
  • Digital control for use with INDEL feature on the I/O
  • 12 per device