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ORCA Series 3 is an established Family of SRAM-based FPGAs from Lattice, with enhancements and innovations geared toward today's high-speed designs and tomorrow's systems on a single chip. This FPGA family is the world's first to embed system-level features like a microprocessor interface and programmable clock manager.
Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the ORCA Series 2 devices, the ORCA Series 3 more than doubles the logic available in each PFU and incorporates system-level features that further reduce logic requirements and increase system speed. ORCA Series 3 devices contain many patented architectural enhancements and are offered in a variety of packages, speed grades, voltages, and temperature ranges.
Family Member Selector Guide
| Vcc |
Device |
FPGA System Gates (K) |
LUTs |
Registers |
Max User RAM (K) |
Max User I/O |
Array Size (PLCs) |
| 2.5V |
OR3L165B |
120-244 |
8,192 |
10,752 |
131 |
326 |
32x32 |
| OR3L225B |
166-340 |
11,552 |
14,820 |
185 |
326 |
38x38 |
| 3.3V |
OR3T20 |
36 |
1,152 |
1,872 |
18 |
192 |
12x12 |
| OR3T30 |
48 |
1,568 |
2,436 |
25 |
224 |
14x14 |
| OR3T55 |
80 |
2,592 |
3,780 |
42 |
288 |
18x18 |
| OR3T80 |
116 |
3,872 |
5,412 |
62 |
342 |
22x22 |
| OR3T125 |
186 |
6,272 |
8,400 |
100 |
448 |
28x28 |
| 5.0V |
OR3C80 |
116 |
3,872 |
5,412 |
62 |
342 |
22x22 |
Features
- Up to 340K FPGA System Gates.
- Up to 448 user I/Os. (OR3LxxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis, when using 3.3 V I/O supply.)
- Twin-quad Programmable Function Unit (PFU) architecture with eight 16-bit Look-Up Tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU.
- Nine user registers per PFU, one following each LUT, plus one extra. All have programmable clock enable and local set/reset, plus a Global Set/Reset (GSRN) that can be disabled per PFU.
- Flexible Input Structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs.
- Fast-carry logic and routing to adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
- SoftWired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU.
- Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay.
- Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source.
- Built-in boundary scan ( IEEE�1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins.
- Enhanced system clock routing for low-skew, highspeed clocks originating on-chip or at any I/O.
- Up to four ExpressCLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing.
- StopCLK feature to glitchlessly stop/start the ExpressCLKs independently by user command.
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Programmable I/O (PIO) has:
- Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zero hold time.
- Capability to (de)multiplex I/O signals.
- Fast access to SLIC for decodes and PAL-like functions.
- Output FF and two-signal function generator to reduce CLK to output propagation delay.
- Fast open-drain drive capability.
- New programmable I/O 3-state FF allows 3-state buffer control signals to be set up a clock cycle early for improved clock to output delays.
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