ORCA Series 2 FPGA

ORCA Series 2 SRAM-based FPGAs include patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources. All devices are offered in a variety of packages, speed grades, and temperature ranges.

ORCA Series 2 FPGAs consist of two basic elements: Programmable Logic Cells (PLCs) and Programmable Input/output Cells (PICs). An array of PLCs is surrounded by PICs. Each PLC contains a Programmable Function Unit (PFU). The PLCs and PICs also contain routing resources and configuration RAM. All logic is done in the PFU. Each PFU contains four 16-bit Look-Up Tables (LUTs) and four latches/Flip-Flops (FFs). The LUTs can be programmed to operate in one of three modes: combinatorial, ripple, or memory. In combinatorial mode, the LUTs can be programmed to realize realize any four-, five-, or six-input logic functions. In ripple mode, the high-speed carry logic is used for arithmetic functions, the multiplier function, or the enhanced data path functions. In memory mode, the LUTs can be used as a 16 x 4 read/write or read-only memory (asynchronous mode or synchronous mode) or a 16 x 2 dual-port memory.

The PLC architecture provides a balanced mix of logic and routing that allows a higher utilized gate/PFU than alternative architectures. The routing resources carry logic signals between PFUs and I/O pads. The routing in the PLC is symmetrical about the horizontal and vertical axes. This improves routability by allowing a bus of signals to be routed into the PLC from any direction. Each PIC is comprised of I/O drivers, I/O pads, and routing resources. Each I/O can be programmed to be either an input, output, or bidirectional signal. Other options include variable output slew rates and pull-up or pull-down resistors. OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.

Features

• Up to 99,400 FPGA system gates.
• Up to 342 user I/Os, 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.
• Four 16-bit look-up tables and four latches/flip-flops per PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or 32-bit (or wider) bus structures
• Eight 3-state buffers per PFU for on-chip bus structures
• Fast on-chip user SRAM has features to simplify RAM design and increase RAM speed:
  • Asynchronous single port: 64 bits/PFU
  • Synchronous single port: 64 bits/PFU
  • Synchronous dual port: 32 bits/PFU
• Improved ability to combine PFUs to create larger RAM structures using write-port enable and 3-state buffers
• Fast, dense multipliers can be created with the multiplier mode (4 x 1 multiplier/PFU):
  • 8 x 8 multiplier requires only 16 PFUs
  • 30% increase in speed
• Flip-flop/latch options to allow programmable priority of synchronous set/reset vs. clock enable
• Enhanced cascadable nibble-wide data path capabilities for adders, subtractors, counters, multipliers, and comparators including internal fast-carry operation
• Innovative, abundant, and hierarchical nibble-oriented routing resources that allow automatic use of internal gates for all device densities without sacrificing performance
• Pinout-compatible with ORCA Series 3 FPGAs
• Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source
• Built-in boundary scan ( IEEE 1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins.
• Multiple configuration options, including simple, low pincount serial ROMs, and peripheral or JTAG modes for In-System Programming (ISP)
• Fast configuration speed (40 MHz).
• Full PCI bus compliance in both 5 V and 3.3 V PCI systems. Pin selectable I/O clamping diodes provide 5 V or 3.3 V PCI compliance and 5 V tolerance.
• High-performance, cost-effective, low-power, 0.3 CMOS technology (OR2TxxA), and 0.25 CMOS technology (OR2TxxB), (four-input Look-Up Table (LUT) delay less than 1.0 ns with -8 speed grade)