Instant-On FPGA Solutions: ispXPGA

The ispXPGA family of FPGA devices allows the creation of high-performance logic designs that are both non-volatile and infinitely re-configurable. Other FPGA solutions force a compromise, being either re-programmable, or reconfigurable, or non-volatile. This FPGA family offers all of these capabilities with a mainstream architecture containing the features required for today's system-level design.

The ispXPGA FPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications and the "E-Series", a high-performance, low-cost FPGA device with no sysHSI functionality.

Note: 8 PLLs with global clocks and low-skew clock nets per device.
* "E-Series" does not support sysHSI.

Features

• New ispXP (eXpanded Programmability): Non-Volatile, Infinitely Reconfigurable
  • Power-up in Microseconds via On-Chip E² Cells for Instant-on Usage
  • Reconfigure SRAM-based FPGA Logic in Milliseconds
  • In-System Programmable
  • No External Configuration Memory Needed for FPGA Configuration
• System-Level Integration
  • 139K to 1.25M System Gates
  • Up to 496 I/Os
  • Up to 414Kb Embedded Memory
• Two Options Available
  • High-performance sysHSI^TM (Standard part number)
  • Low-cost, no sysHSI ("E-Series" part number)
• sysHSI SERDES for up to 800Mbps Serial Communications
• High Performance Logic Blocks (PFUs)
• Block and Distributed Memory
• Variable-Length Interconnect Routing
• sysCLOCK^TM PLLs for Clock Management
• sysIO^TM for High Performance Interfacing
• 1.8V, 2.5V, and 3.3V Operation

ispXPGA Programming/Configuration

• Auto-configure FPGA at Power-up in µSec
• Reconfigure FPGA In-System in mSec
• Reprogram FPGA During System Operation
• Configure from On-Chip E² or CPU
• Set Security Bits to Prevent Readback
• No External Configuration Memory

Lattice IP Cores and Reference Designs

ispXPGA design is supported by a variety of pre-tested, reusable functions optimized for the ispXPGA architecture. Browse the See Also section of this page for ispLeverCORE Connection Partner links.

Lattice IP Cores

• Convolutional Encoder
• DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
• Ethernet MAC Cores
• Interleaver/De-Interleaver
• Multi-channel DMA Controller
• Parallel FIR Filter
• Reed-Solomon Decoder
• Reed-Solomon Encoder
• Serial FIR Filter
• Turbo Decoder
• Turbo Encoder
• Viterbi Decoder

Lattice Reference Designs

• 8b/10b Encoder/Decoder

ispXPGA FPGA Evaluation Boards

The ispXPGA Evaluation Board is a complete hardware kit that allows the user to program, evaluate, and de-bug a design for the Lattice ispXPGA architecture.

View the ispXPGA Evaluation Board webpage.

For information regarding ispLEVER software, supporting ispXPGA and ispXPLD device design, contact your local Lattice field sales representative.

The World's First FPGA to Offer Non-Volatility and Reconfigurability