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FPGA (Field Programmable Gate Array) solutions from Lattice deliver unique features, high performance, and excellent value for FPGA designs.
High-Value FPGA
- Lattice ECP3 FPGA devices offers the industry's lowest power consumption and price of any SERDES-capable FPGA device with advanced features multi-protocol 3.2G SERDES with XAUI jitter compliance, pre-engineered source synchronous support (including DDR1/2/3), cascadable DSP blocks, high density on-chip memory and up to 149K LUTS.
- LatticeECP2 FPGA devices combine a low cost FPGA fabric with advanced features such as pre-engineered source synchronous support (including 400Mbps DDR2), high-performance embedded DSP blocks that provide up to 33GMACs of DSP bandwidth and enhanced configuration including bitstream encryption ("S-Series" Only), dual boot and TransFR I/O.
- LatticeECP2M FPGA devices provide the same feature set as the LatticeECP2 family but have embedded 3.125Gbps SERDES and increase memory capacity to 5.3Mbits and DSP capability to 63GMACs.
- LatticeEC (EConomy) FPGA devices optimize features, performance, and cost: pre-engineered 400 Mbps DDR memory interfaces, low-cost SPI Flash FPGA configuration, mainstream LUT-4 based FPGA fabric.
- LatticeECP-DSP (EConomyPlus-DSP) FPGA devices combine the LatticeEC FPGA fabric with high-performance embedded DSP blocks: DSP bandwidth up to 10 GMACs.
High Performance FPGA
- LatticeSC (System Chip) FPGA couples the industry's fastest FPGA fabric with system level features like 2Gbps PURESPEED I/O, 32 channels of SERDES and pre-engineered embedded IP using on-chip structured ASIC blocks for best-in-class programmable connectivity solutions.
Non-Volatile FPGA
- LatticeXP2 FPGA devices utilize an underlying LatticeECP2 fabric combined with a low-cost 90nm Flash FPGA technology in an Architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits such as instant-on, small footprint, on-chip storage with FlashBAK™ embedded block memories, Serial TAG memory and design security. LatticeXP2 devices also support Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies.
- Lattice's MachXO PLDs provide a versatile, non-volatile logic solution for low density applications. Combining an optimized look-up table (LUT) architecture with low-cost embedded flash process technology, the instant-on, easy to use MachXO PLDs are ideal for general purpose I/O expansion, control, bus bridging and power-up management functions.
- LatticeXP (eXpanded Programmability) FPGA devices use an underlying LatticeEC architecture combined with 130nm Flash technology to deliver instant-on, small footprint and design security.
- Lattice's ispXPGA FPGA devices combine E2 non-volatile cells with a LUT-4 based FPGA fabric.
LatticeECP3 FPGA Product Family Selector Guide
| Device |
SERDES
Channels (Max) |
18 x 18 Mult. |
LUTs (K) |
Dist. RAM (K) |
EBR Block SRAM (K) |
EBR SRAM Blocks |
Max User I/O |
PLLs/
DLLS |
| ECP3-17 |
4 |
24 |
17 |
36 |
700 |
38 |
222 |
2/2 |
| ECP3-35 |
4 |
68 |
33 |
68 |
1327 |
72 |
310 |
4/2 |
| ECP3-70 |
12 |
128 |
67 |
145 |
4420 |
240 |
490 |
10/2 |
| ECP3-95 |
12 |
128 |
92 |
188 |
4420 |
240 |
490 |
10/2 |
| ECP3-150 |
16 |
320 |
149 |
303 |
6850 |
372 |
586 |
10/2 |
LatticeECP2M (including "S-Series") FPGA Product Family Selector Guide
| Device |
SERDES
Channels (Max) |
18 x 18 Mult. |
LUTs (K) |
Dist. RAM (K) |
EBR Block SRAM (K) |
EBR SRAM Blocks |
Max User I/O |
PLLs/
DLLS |
| ECP2M-20 |
4 |
24 |
19 |
41 |
1217 |
66 |
304 |
8/2 |
| ECP2M-35 |
4 |
32 |
34 |
71 |
2101 |
114 |
410 |
8/2 |
| ECP2M-50 |
8 |
88 |
48 |
101 |
4147 |
225 |
410 |
8/2 |
| ECP2M-70 |
16 |
96 |
67 |
145 |
4534 |
246 |
436 |
8/2 |
| ECP2M-100 |
16 |
168 |
85 |
202 |
5308 |
288 |
616 |
8/2 |
LatticeECP2 (including "S-Series") FPGA Product Family Selector Guide
| Device |
sysDSP Blocks |
18 x 18 Mult. |
LUTs (K) |
Dist. RAM (K) |
EBR Block SRAM (K) |
EBR SRAM Blocks |
Max User I/O |
PLLs/
DLLS |
| ECP2-6 |
3 |
12 |
6 |
12 |
55 |
3 |
190 |
2/2 |
| ECP2-12 |
6 |
24 |
12 |
24 |
221 |
12 |
297 |
2/2 |
| ECP2-20 |
7 |
28 |
21 |
42 |
277 |
15 |
402 |
2/2 |
| ECP2-35 |
8 |
32 |
32 |
65 |
332 |
18 |
450 |
2/2 |
| ECP2-50 |
18 |
72 |
48 |
96 |
387 |
21 |
500 |
4/2 |
| ECP2-70 |
22 |
88 |
68 |
136 |
1106 |
60 |
583 |
6/2 |
LatticeECP and EC (including "S-Series") FPGA Product Family Selector Guide
| Device |
sysDSP Blocks* |
18 x 18 Mult.* |
LUTs (K) |
Dist. RAM (K) |
EBR Block SRAM (K) |
EBR SRAM Blocks |
Max User I/O |
PLLs |
| EC1 |
- |
- |
1.5 |
6 |
18 |
2 |
112 |
2 |
| EC3 |
- |
- |
3.1 |
12 |
55 |
6 |
160 |
2 |
| ECP6/EC6 |
4 |
16 |
6.1 |
25 |
92 |
10 |
224 |
2 |
| ECP10/EC10 |
5 |
20 |
10.2 |
41 |
277 |
30 |
288 |
4 |
| ECP15/EC15 |
6 |
24 |
15.4 |
61 |
350 |
38 |
352 |
4 |
| ECP20/EC20 |
7 |
28 |
19.7 |
79 |
424 |
46 |
400 |
4 |
| ECP33/EC33 |
8 |
32 |
32.8 |
131 |
535 |
58 |
496 |
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* ECP Devices only
LatticeSC FPGA Product Family Selector Guide
| Device |
SERDES Channels (Max) |
Structured ASIC Blocks (Max) |
LUTs (K) |
Dist. RAM (Mbits) |
EBR Block SRAM (Mbits) |
EBR SRAM Blocks |
Max User I/O |
PLLs/DLLs |
| LFSC15 |
8 |
4 |
15.2 |
0.24 |
1.03 |
56 |
300 |
8/12 |
| LFSC25 |
16 |
6 |
25.4 |
0.41 |
1.92 |
104 |
484 |
8/12 |
| LFSC40 |
16 |
10 |
40.4 |
0.65 |
3.98 |
216 |
562 |
8/12 |
| LFSC80 |
32 |
10 |
80.1 |
1.28 |
5.68 |
308 |
904 |
8/12 |
| LFSC115 |
32 |
12 |
115.2 |
1.84 |
7.80 |
424 |
942 |
8/12 |
LatticeXP2 FPGA Product Family Selector Guide
| Device |
sysDSP Blocks |
18 x 18 Mult. |
LUTs (K) |
Dist. RAM (K) |
EBR Block SRAM (K) |
EBR SRAM Blocks |
Max User I/O |
PLLs |
| XP2-5 |
3 |
12 |
5 |
10 |
166 |
9 |
172 |
2 |
| XP2-8 |
4 |
16 |
8 |
18 |
221 |
12 |
201 |
2 |
| XP2-17 |
5 |
20 |
17 |
35 |
276 |
15 |
358 |
4 |
| XP2-30 |
7 |
28 |
29 |
56 |
387 |
21 |
472 |
4 |
| XP2-40 |
8 |
32 |
40 |
83 |
885 |
48 |
540 |
4 |
MachXO Product Family Selector Guide
| Family |
PLLs |
LUTs |
EBR SRAM Blocks |
EBR Block SRAM (K) |
Dist. RAM (K) |
Max User I/O |
| LCMXO256 |
0 |
256 |
0 |
0 |
2.0 |
78 |
| LCMXO640 |
0 |
640 |
0 |
0 |
6.1 |
159 |
| LCMXO1200 |
1 |
1200 |
1 |
9 |
6.4 |
211 |
| LCMXO2280 |
2 |
2280 |
3 |
27 |
7.7 |
271 |
LatticeXP FPGA Product Family Selector Guide
| Device |
LUTs (K) |
Distributed RAM (K) |
EBR Block SRAM (K) |
Number of EBR SRAM Blocks |
Max User I/O |
PLLs |
| LFXP3 |
3.1 |
12 |
54 |
6 |
136 |
2 |
| LFXP6 |
5.8 |
23 |
72 |
8 |
188 |
2 |
| LFXP10 |
9.7 |
39 |
216 |
24 |
244 |
4 |
| LFXP15 |
15.4 |
61 |
324 |
36 |
300 |
4 |
| LFXP20 |
19.7 |
79 |
396 |
44 |
340 |
4 |
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With its huge simultaneous announcement of 90nm-based high-performance and low-cost FPGAs, Lattice (along with fab partner Fujitsu) has shown that they are serious about the FPGA game.
Kevin Morris, Editor, FPGA Journal
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