FPGA (Field Programmable Gate Array) solutions from Lattice deliver unique features, high performance, and excellent value for FPGA designs.
- The LatticeECP3 FPGA Family offers low cost and low power with advanced features including multi-protocol 3.2G SERDES with XAUI jitter compliance, pre-engineered source synchronous support (including DDR1/2/3), cascadable DSP blocks, high density on-chip memory and up to 149K LUTS.
- LatticeECP2 FPGA devices combine a low cost FPGA fabric with advanced features such as pre-engineered source synchronous support (including 400Mbps DDR2), high-performance embedded DSP blocks that provide up to 33GMACs of DSP bandwidth and enhanced configuration including bitstream encryption ("S-Series" Only), dual boot and TransFR I/O.
- LatticeECP2M FPGA devices provide the same feature set as the LatticeECP2 family but have embedded 3.125Gbps SERDES and increase memory capacity to 5.3Mbits and DSP capability to 63GMACs.
- LatticeSC (System Chip) FPGA couples the industry's fastest FPGA fabric with system level features like 2Gbps PURESPEED I/O, 32 channels of SERDES and pre-engineered embedded IP using on-chip structured ASIC blocks for best-in-class programmable connectivity solutions.
- Lattice's iCE40 Los Angeles mobileFPGA™ family is designed for sensor management, video and imaging, custom connectivity, and memory/storage expansion for Custom Mobile Device™ solutions. Fabricated on a 40-nm low-power, standard CMOS process, the Los Angeles family has been optimized for consumer applications.
- Lattice's MachXO2 family offers designers of low-density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, MachXO2 devices offer designers a "Do-it-All PLD" for system and consumer designs.
- Lattice's MachXO PLDs provide a versatile, non-volatile logic solution for low density applications. Combining an optimized look-up table (LUT) architecture with low-cost embedded flash process technology, the instant-on, easy to use MachXO PLDs are ideal for general purpose I/O expansion, control, bus bridging and power-up management functions.
- LatticeXP2 FPGA devices utilize an underlying LatticeECP2 fabric combined with a low-cost 90nm Flash FPGA technology in an Architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits such as instant-on, small footprint, on-chip storage with FlashBAK™ embedded block memories, Serial TAG memory and design security. LatticeXP2 devices also support Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies.
LatticeECP3 FPGA Product Family Selector Guide
| |
ECP3-17 |
ECP3-35 |
ECP3-70 |
ECP3-95 |
ECP3-150 |
| SERDES Channels (Max) |
4 |
4 |
12 |
12 |
16 |
| 18 x 18 Mult. |
24 |
68 |
128 |
128 |
320 |
| LUTs (K) |
17 |
33 |
67 |
92 |
149 |
| Dist. RAM (K) |
36 |
68 |
145 |
188 |
303 |
| EBR Block SRAM (K) |
700 |
1327 |
4420 |
4420 |
6850 |
| EBR SRAM Blocks |
38 |
72 |
240 |
240 |
372 |
| Max User I/O |
222 |
310 |
490 |
490 |
586 |
| PLLs/DLLS |
2/2 |
4/2 |
10/2 |
10/2 |
10/2 |
LatticeECP2M (including "S-Series") FPGA Product Family Selector Guide
| |
ECP2M-20 |
ECP2M-35 |
ECP2M-50 |
ECP2M-70 |
ECP2M-100 |
| SERDES Channels (Max) |
4 |
4 |
8 |
16 |
16 |
| 18 x 18 Mult. |
24 |
32 |
88 |
96 |
168 |
| LUTs (K) |
19 |
34 |
48 |
67 |
85 |
| Dist. RAM (K) |
41 |
71 |
101 |
145 |
202 |
| EBR Block SRAM(K) |
1217 |
2101 |
4147 |
4534 |
5308 |
| EBR SRAM Blocks |
66 |
114 |
225 |
246 |
288 |
| Max User I/O |
304 |
410 |
410 |
436 |
616 |
| PLLs/DLLS |
8/2 |
8/2 |
8/2 |
8/2 |
8/2 |
LatticeECP2 (including "S-Series") FPGA Product Family Selector Guide
| |
ECP2-6 |
ECP2-12 |
ECP2-20 |
ECP2-35 |
ECP2-50 |
ECP2-70 |
| sysDSP Blocks |
3 |
6 |
7 |
8 |
18 |
22 |
| 18 x 18 Mult. |
12 |
24 |
28 |
32 |
72 |
88 |
| LUTs (K) |
6 |
12 |
21 |
32 |
48 |
68 |
| Dist. RAM (K) |
12 |
24 |
42 |
65 |
96 |
136 |
| EBR Block SRAM (K) |
55 |
221 |
277 |
332 |
387 |
1106 |
| EBR SRAM Blocks |
3 |
12 |
15 |
18 |
21 |
60 |
| Max User I/O |
190 |
297 |
402 |
450 |
500 |
583 |
| PLLs/DLLS |
2/2 |
2/2 |
2/2 |
2/2 |
4/2 |
6/2 |
LatticeSC FPGA Product Family Selector Guide
| |
LFSC15 |
LFSC25 |
LFSC40 |
LFSC80 |
LFSC115 |
| SERDES Channels (Max) |
8 |
16 |
16 |
32 |
32 |
| Structured ASIC Blocks (Max) |
4 |
6 |
10 |
10 |
12 |
| LUTs (K) |
15.2 |
25.4 |
40.4 |
80.1 |
115.2 |
| Dist. RAM (Mbits) |
0.24 |
0.41 |
0.65 |
1.28 |
1.84 |
| EBR Block SRAM (Mbits) |
1.03 |
1.92 |
3.98 |
5.68 |
7.80 |
| EBR SRAM Blocks |
56 |
104 |
216 |
308 |
424 |
| Max User I/O |
300 |
484 |
562 |
904 |
942 |
| PLLs/DLLs |
8/12 |
8/12 |
8/12 |
8/12 |
8/12 |
iCE40 Product Family Selector Guide
| |
1K |
4K |
8K |
| PLLs |
1 |
2 |
2 |
| LUTs |
1280 |
3520 |
7680 |
| EBR (Kbits) |
64 |
80 |
128 |
| Max User I/O |
97 |
167 |
206 |
MachXO2 Product Family Selector Guide
| |
XO2-256 |
XO2-640 |
XO2-1200 |
XO2-2000 |
XO2-4000 |
XO2-7000 |
| PLLs |
0 |
0 |
1 |
1 |
2 |
2 |
| LUTs |
256 |
640 |
1280 |
2112 |
4320 |
6864 |
| EBR (Kbits) |
0 |
18 |
64 |
74 |
92 |
240 |
| UFM (Kbits) |
0 |
24 |
64 |
80 |
96 |
256 |
| Dist. RAM (Kbits) |
2 |
5 |
10 |
16 |
34 |
54 |
| Max User I/O |
56 |
80 |
108 |
207 |
279 |
335 |
| Hardened I2C, SPI, Timer/Counter |
 |
 |
 |
 |
 |
 |
MachXO Product Family Selector Guide
| |
XO-256 |
XO-640 |
XO-1200 |
XO-2280 |
| PLLs |
0 |
0 |
1 |
2 |
| LUTs |
256 |
640 |
1200 |
2280 |
| EBR SRAM Blocks |
0 |
0 |
1 |
3 |
| EBR Block SRAM (K) |
0 |
0 |
9 |
27 |
| Dist. RAM (K) |
2.0 |
6.1 |
6.4 |
7.7 |
| Max User I/O |
78 |
159 |
211 |
271 |
LatticeXP2 FPGA Product Family Selector Guide
| |
XP2-5 |
XP2-8 |
XP2-17 |
XP2-30 |
XP2-40 |
| sysDSP Blocks |
3 |
4 |
5 |
7 |
8 |
| 18 x 18 Mult. |
12 |
16 |
20 |
28 |
32 |
| LUTs (K) |
5 |
8 |
17 |
29 |
40 |
| Dist. RAM (K) |
10 |
18 |
35 |
56 |
83 |
| EBR Block SRAM (K) |
166 |
221 |
276 |
387 |
885 |
| EBR SRAM Blocks |
9 |
12 |
15 |
21 |
48 |
| Max User I/O |
172 |
201 |
358 |
472 |
540 |
| PLLs |
2 |
2 |
4 |
4 |
4 |