FPGA Devices

FPGA (Field Programmable Gate Array) solutions from Lattice deliver unique features, high performance, and excellent value for FPGA designs.

• The LatticeECP3 FPGA Family offers low cost and low power with advanced features including multi-protocol 3.2G SERDES with XAUI jitter compliance, pre-engineered source synchronous support (including DDR1/2/3), cascadable DSP blocks, high density on-chip memory and up to 149K LUTS.
• LatticeECP2 FPGA devices combine a low cost FPGA fabric with advanced features such as pre-engineered source synchronous support (including 400Mbps DDR2), high-performance embedded DSP blocks that provide up to 33GMACs of DSP bandwidth and enhanced configuration including bitstream encryption ("S-Series" Only), dual boot and TransFR I/O.
• LatticeECP2M FPGA devices provide the same feature set as the LatticeECP2 family but have embedded 3.125Gbps SERDES and increase memory capacity to 5.3Mbits and DSP capability to 63GMACs.

• LatticeSC (System Chip) FPGA couples the industry's fastest FPGA fabric with system level features like 2Gbps PURESPEED I/O, 32 channels of SERDES and pre-engineered embedded IP using on-chip structured ASIC blocks for best-in-class programmable connectivity solutions.

• Lattice's iCE40 Los Angeles mobileFPGA™ family is designed for sensor management, video and imaging, custom connectivity, and memory/storage expansion for Custom Mobile Device™ solutions. Fabricated on a 40-nm low-power, standard CMOS process, the Los Angeles family has been optimized for consumer applications.
• Lattice's MachXO2 family offers designers of low-density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, MachXO2 devices offer designers a "Do-it-All PLD" for system and consumer designs.
• Lattice's MachXO PLDs provide a versatile, non-volatile logic solution for low density applications. Combining an optimized look-up table (LUT) architecture with low-cost embedded flash process technology, the instant-on, easy to use MachXO PLDs are ideal for general purpose I/O expansion, control, bus bridging and power-up management functions.
• LatticeXP2 FPGA devices utilize an underlying LatticeECP2 fabric combined with a low-cost 90nm Flash FPGA technology in an Architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits such as instant-on, small footprint, on-chip storage with FlashBAK™ embedded block memories, Serial TAG memory and design security. LatticeXP2 devices also support Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies.

MachXO2 Product Family Selector Guide

	XO2-256	XO2-640	XO2-1200	XO2-2000	XO2-4000	XO2-7000
PLLs	0	0	1	1	2	2
LUTs	256	640	1280	2112	4320	6864
EBR (Kbits)	0	18	64	74	92	240
UFM (Kbits)	0	24	64	80	96	256
Dist. RAM (Kbits)	2	5	10	16	34	54
Max User I/O	56	80	108	207	279	335
Hardened I2C, SPI, Timer/Counter