Flexible sysIO Buffers & sysCLOCK PLLs

Flexible sysIO Buffers

• sysIO interface support
  • LVCMOS/LVTTL
    • Hot-socketing capable
    • Programmable slew rate
    • Programmable drive strength
    • Programmable pull-up, pull-down, bus friendly
    • Programmable open drain
  • PCI, LVDS, SSTL, HSTL, Differential HSTL, Differential SSTL, LVPECL, BLVDS, RSDS
  • 700Mbps+ I/O buffers
  • 400Mbps DDR memory interface
• Eight I/O banks per device
• Output standard support dependent on Vccio
• Referenced inputs dependent on Vref
• LVCMOS Inputs
  • 12, 25 & 33 independent of Vccio
  • 15 & 18 dependent on Vccio
• Multiple compatible I/O standards in a bank

sysCLOCK PLLs

• Frequency range 25 to 420MHz
• Low output period jitter (+/-100ps)
• Programmable phase/duty cycle (45 degree steps)
• Programmable M, N, V and K counters
• Internal and External Feedback