LatticeECP4 MACO Communication Engines

The LatticeECP4 MACO Communication Engines are functional logic blocks implemented using dedicated islands of ASIC resources within the FPGA. The proprietary MACO (Multiple Access Cost Optimized) technology offers up to 10X the power and cost reduction of similar implementations in other FPGA fabrics. The MACO Communication Engines perform efficient processing of popular communication protocols, such as PCI Express 2.1, 10 Gigabit Ethernet MAC, Gigabit Ethernet MAC and Tri-speed Ethernet MAC, as well as Serial Rapid I/O (SRIO) 2.1.  The LatticeECP4 is the only  mid-range FPGA with a hardened Serial RapidIO 2.1 interface for building the latest generation wireless systems.

The MACO Communication Engines have been designed and characterized to meet the rigorous data and control plane timing requirements of each protocol. These engines provide industry-compliant OSI Layer-2 (link layer) functionality for each protocol as well as additional OSI Layer-1 functionality. The configurable MACO Engines can be customized by embedding proprietary code in the surrounding FPGA logic fabric. The LatticeECP4 FPGAs provide a generic Application Layer interface between the MACO Engines and the surrounding logic fabric. Designers can also access network control and statsitics vectors within the MACO Engines.

The versatile MACO Communication Engines are seamlessly integrated with 6G CEI-Compliant SERDES/PCS Blocks to offer complete high bandwidth network interfaces. The combination of SERDES/PCS, Communication Engines and programmable logic fabric is ideal for completing complex serial protocol-based designs with lower cost, power and footprint, while accelerating time to market. The larger devices contain all the Communications Engines found within the smaller ones, plus an additional Engine. Lattice Diamond 1.4 design software offers an easy-to-use SystemPlanner Tool to help customers efficiently integrate MACO Communication Engines with SERDES/PCS Blocks and the surrounding logic fabric.

The table below lists the number of SERDES/PCS Blocks and MACO Communication Engines available for each member of the LatticeECP4 FPGA family. The LatticeECP4 FPGAs can have up to 14 MACO Engines for high Ethernet port density networking equipment.

*  Each unused 10G MAC can be used as 4 additional Tri-Speed MACs
**  Supports 2.5G Ethernet.

For more information on how LatticeECP4 SERDES/PCS Blocks and MACO Communication Engines can enable you to design next generation wireline and wireless systems, please review the LatticeECP4 MACO Communication Engines Whitepaper.