LatticeECP4 High Speed Source Synchronous I/Os

In Detail

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The LatticeECP4 offers a wide range of system I/Os (GIGA sysIOs) to connect the FPGA to other devices within a system. These range from single-ended, differential, to serial I/Os with embedded clock data recovery (CDR) circuits, and high-speed memory interfaces (DDR, DDR2, and DDR3).

GIGA sysIOs

Differential I/Os with Data Rates up to 1.25 Gbps
Proprietary Innovations in Low Cost Devices for High Speed Interfaces
- Data Eye Monitor for dynamic input alignment
- I/O Expansion Logic to widen the databus and reduce clock
- Circuit to mitigate inter-symbol interference (ISI)
- Useful for DDR/DDR2/DDR3, SPI 4.2, SGMII, and Video Interfaces
GIGA sysIOs with Embedded CDRs
- Up To 36 Embedded Clock Data Recovery Circuits
- Implement Gigabit Ethernet and SGMII using GIGA sysIOs
- Conserve SERDES for 2.5G and Higher Applications
High Speed External Memory Interfaces
- 1066 Mbps DDR3 Interface (DDR, DDR2, and DDR3)
- QDR I/II
- RLDRAM I/II
Broad Range of IO standards
- LVCMOS 3.3/2.5/1.8/1.5/1.2
- SSTL 3.3/2.5/1.8/1.5 & HSTL-15 & HSTL-18
- LVDS, Bus-LVDS, RSDS, MLVDS & LVPECL
- PCI

High Speed Source Synchronous Interfaces
- 7:1 / 8:1 LVDS
- ADC / DAC
Built-in Voltage Level Shifters
Programmable Slew Rates
On-Chip Termination

GIGA sysIO Cell Block Diagram

GIGA sysIOs with Embedded CDRs

The LatticeECP4 FPGAs contain up to 36 embedded clock data recovery (CDR) circuits, which can be combined with the differential I/Os to implement GIGA serial interfaces with speeds up to 1.25 Gbps. In particular, GIGA serial I/Os can be used to implement popular Gigabit Ethernet and SGMII interfaces. The GIGA serial I/Os can also be directly connected to built-in MACO Communication Engines. The ability to implement Gigabit Ethernet interfaces using general purpose I/Os conserves the 6G SERDES for higher bandwidth interfaces and enables designers to build high port density communication equipment using the low cost LatticeECP4 FPGAs.

The figure below illustrates the functional block diagram of a LatticeECP4 CDR circuit, where the phase relationship of the receive data is monitored against a recovered clock. Using soft IP specifically designed to dynamically monitor and control the Clock Alignment logic, designers can establish and maintain a valid receive data window. To learn more about the capabilities of pre-engineered source synchronous I/Os in LatticeECP4 FPGAs, download the LatticeECP4 High Speed I/O Whitepaper.