LatticeECP4 DSP Blocks

The LatticeECP4 FPGA family features powerful digital signal processing (DSP) blocks with 18x18 multipliers and cascadable ALUs.  The unique "Booster Logic" allows LatticeECP4 DSP blocks to run at twice the speed of the logic fabric. In addition, the LatticeECP4 DSP architecture leverages the symmetry of common filters to process twice as many signals. The combination of these two new innovations increases the throughput of LatticeECP4 DSPs 6X compared to the previous generation LatticeECP3 FPGAs. The flexible 18x18 multipliers can be split into 9x9 or combined into 36x36 to perfectly match customers’ application requirements. Moreover, up to 480 multipliers can be cascaded together to build complex filters for wireless Remote Radio Heads (RRH), MIMO-based RF antenna solutions and video processing applications. The attached figure illustrates two slices of the LatticeECP4 DSP which constitute a DSP block.

Power sysDSP Blocks

• Booster Logic
  • Leverages TDM techniques to enable DSP Blocks to run at twice (2X) the speed of the FPGA logic fabric
  • Maintains effective usage of low cost logic fabric 
• Pre-Adder Logic
  • Leverages coefficient symmetry of common filters to provide 2X performance improvement
  • Coefficient symmetry is a common attribute of most FIR filters 
• Powerful 4th Generation sysDSP Architecture
  • Dual-multiplier architecture
  • Fully cascadable blocks 
  • Backward compatible with LatticeECP3 sysDSP blocks
• Programmable Multipliers
  • Two 18x18, four 9x9 per slice
  • Single 36x36 across two adjacent slices
  • Single precision floating point arithmetic
  • 18x36 MAC & 18x18 MMAC modes
• 54-bit Cascadable ALU
  • Rounding & truncation
  • Neighboring ALU output chainable as third input for ternary ALU operations
• High performance modes
  • MULT (Multiplier)
  • MAC (Multiplier Accumulate)
  • MMAC (Multiplier Multiplier Accumulate)
  • MULTADDSUB (Multiplier Add/Subtract)
  • MULTADDSUBSUM (Multiply Add/Subtract and SUM)
  • SLICE (Fully configurable sysDSP slice used for advanced functions)
  • Adder Tree
  • Wide Mux
• Up to 480 multipliers (18x18)
  • Effectively the same throughput as 1920 LatticeECP3 symmetric multipliers
  • Effectively the same throughput as 960 LatticeECP3 asymmetric multipliers
  • Based on innovative Booster Logic and Pre-Adder Logic implemented in Power sysDSP blocks

Download the LatticeECP4 DSP Architecture Whitepaper for an in-depth discussion about the architecture and capabilities of the LatticeECP4 DSP Blocks.

Wireless Applications

The LatticeECP4 DSP is an efficient architecture for multiplication-intensive wireless and video signal processing applications. One multiplication-intensive wireless application is a Remote Radio Unit (RRU) board. Download the LatticeECP4 DSP Wireless Applications Whitepaper to learn how LatticeECP4's unique DSP capabilities can be used to implement a compute-intensive RRU board using LatticeECP4 low cost, low power FPGAs.

High Performance LatticeECP4 DSP-Based Filter Designs

Lattice has developed several examples of filter designs to demonstrate the capabilities of LatticeECP4 DSP technology. Two of the DSP design examples are highlighted below:

• Direct Form 64-Tap FIR Filter: In the direct form FIR filter, the input samples are shifted into a shift register queue and each shift register is connected to a multiplier. The products from the multipliers are added together to get the FIR filter’s output sample. This example shows a 64-tap FIR filter using 16 sysDSP blocks and approximately 480 slices in the LatticeECP4 FPGA.

• Polyphase Interpolator FIR Filter Designs: The polyphase interpolation filter implements the computationally efficient 1-to-P interpolation filter where P is an integer greater than 1. The example below shows a design with an interpolation by 16 that uses 128 taps. This requires 8 polyphase filters (sub-filters) with 16 coefficients each.