The LatticeECP4 FPGA family combines a high-performance FPGA fabric, high-performance I/Os and up to 12 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. Each channel of PCS logic contains dedicated transmit and receive circuitry for high speed, full duplex serial data transfer of up to 6 Gbps. The PCS logic in each channel can be configured to support an array of popular data protocols including GbE, XAUI, PCI Express PIPE, SRIO, CPRI, OBSAI, SD-SDI and HD-SDI. In addition, the protocol-based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high speed data interface.
Each SERDES channel consumes less than 175mW of power at 6 Gbps, enabling the lowest power implementation of high speed Serial Protocols. The built-in pre-emphasis and equalization circuitry ensure low BER and a high quality eye diagram as illustrated on the right:
The following table summarizes the various serial protocols supported by LatticeECP4 SERDES and the protocol processing performed by hard-wired MACO Communication Engines.
The Physical Coding Sub-layer (PCS) offers a low latency variation option which enables a smaller, cleaner CPRI implementation.
© Lattice Semiconductor Corporation 2012
