Serial RapidIO Solutions Using LatticeECP3

The Serial RapidIO (SRIO) interconnect architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect between NPUs (network processing units), CPUs (central processing units), and DSPs (digital signal processors). It enables chip-to-chip, board-to-board, and system-to-system communication and is targeted at the wireless infrastructure, backplanes, embedded/industrial control, storage, military/aerospace, medical and image processing markets.

The LatticeECP3 FPGA based fully integrated evaluation and demonstration platform built on the industry standard Advanced Mezzanine Card (AMC) form factor supports Lattice’s Serial RapidIO 2.1 endpoint IP core and offers users the ability to investigate the low cost, low power programmable Serial RapidIO 2.1 solution.

Serial RapidIO 2.1 Endpoint IP Core

Serial RapidIO 2.1 Endpoint IP Core can be used for processor bridging, control plane interfaces and bridging to legacy interfaces. The core architecture for the Serial RapidIO 2.1 IP core includes the following features:

• Compliant with Rev. 2.1 specification; backward compatible with Rev 1.3
• Up to 3.125Gbps in 1x, 2x and 4x lane configurations
• Implements physical layer, transport layer, maintenance transaction handling and error management extensions

LatticeECP3 AMC Evaluation Platform

LatticeECP3 AMC Evaluation Platform consists of

• LatticeECP3 AMC Evaluation board
• Associated cables
• AMC interface card
• Demonstration bitstreams and files

Download Documents

• Serial RapidIO 2.1 IP Core - User Guide
• LatticeECP3 AMC Evaluation board - User Guide
• SRIO Demonstration - User Guide
• TI 6482 Digital Signal Processor Interoperability with LatticeECP3
• LatticeECP3 - product brief
• Lattice Wireless Solutions - product brief

Learn More About The LatticeECP3 FPGA

• LatticeECP3 - datasheet
• Contact your local Lattice Sales office for a demonstration