Broad I/O Interface Support

Flexible sysIO Buffers

The LatticeECP3 sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards.  The sysIO interface contains multiple Programmable I/O Cell (PIC) blocks.

Broad Range of IO standards LVDS LVCMOS, LVTTL, LVPECL HSTL, SSTL Class I & II PCI External Memory Interfaces DDR, DDR2, DDR3 QDR I/II RLDRAM I/II

High Speed Source Synchronous Interfaces 7:1 LVDS ADC/DAC Six General Purpose I/O Banks Per Device Multiple compatible I/O standards in a bank On-Chip Termination Programmable Slew Rates

LatticeECP3 I/O Cell Block Diagram

Source Synchronous Interface

Designers are increasingly using source synchronous interfaces driven by many factors such as the need to use low cost DDR1/2/3 DRAM memory, the desire to interface with high-speed ADCs and DACs or the need to interface with a number of communication standards.  The I/O cells in the LatticeECP3 devices contain a number of pre-engineered elements to allow the easy implementation of these source synchronous interfaces.

• 800Mbps DDR3 memory interfaces with built-in read/write leveling
• 1Gbps LVDS I/O, with Input Delay Blocks, allows interfacing to high performance ADC/DACs
• 1:4 & 4:1 gearbox to Match I/O Speed with FPGA Fabric
• DDR to SDR conversion
• DQS alignment
• Precision DQS/Strobe Delay Control
• Dedicated DDR Registers (For Mux and Demuxing)
• Automatic DQS to System Clock Transfer
• Low Skew Edge Clocks