Overview
The LatticeECP3 DDR3 demo demonstrates the functionality of the Lattice DDR3 IP core at a speed of 400 MHz (800 Mbps) using the LatticeECP3 I/O Protocol Board. The DDR3 demo design consists of two major parts:
- DDR3 controller IP core: The demo has been designed to support the parameterized DDR3 data bus widths (8-, 16-, 32-, and 64-bit configurations). The user logic is also parameterized by the core parameter file. A DDR3 IP core configuration file for the 64-bit data width is provided in the demo package.
- User Logic Block provides the following functions: State machine programs the mode registers and controls DDR3 read and write operations, address generation, write data generation, read data validation, and control and observation
Downloads
| User Guide |
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| Source Code |
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© Lattice Semiconductor Corporation 2012
