LatticeECP3 CPRI Demo

Overview

The LatticeECP3 CPRI demo has been designed to demonstrate the performance of the LatticeECP3 PCS with the CPRI IP core at 1.228/2.457/3.072 Gbps.  The CPRI Demo Design is a single-channel CPRI core with data generator/checker. The PCS serializes the data in the transmit direction, and de-serializes it in the receive direction.

• For the Radio Equipment Control (REC) standalone loopback demo, the encoded serial data stream is looped back externally via I/O buffer serial loopback or via cables using the on-board SMA connectors.  In the CPRI REC standalone loopback demo, only one evaluation board is needed to run the loopback test.

• For the REC-RE demo, two LatticeECP3 Serial Protocol Evaluation Boards are required. On the REC side, the tx side serial data stream is generated in the FPGA and run from the local system clock. The tx data is connected through SMA cables to the Radio Equipment (RE) Rx side on the second LatticeECP3 Serial Protocol Evaluation Board. The RE receives the data from the REC and the recovered clock is then used to drive the RE Tx data traffic generation circuit completing the “loop timing”.

Downloads

User Guide
Source Code