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sysDSP Blocks

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DSP Application Space Continues To Expand

The applications of Digital Signal Processing (DSP) continue to expand, driven by trends such as the increased use of video and still images and the demand for increasingly reconfigurable systems such as Software Defined Radio (SDR).  Many of these applications combine the need for significant DSP processing with cost sensitivity, creating demand for high-performance, low-cost DSP solutions.

In order to meet the increasing market demand, the processing elements and their supporting hardware platforms must be able to provide increased calculation throughput without the cost of additional latency.  For example, in the 3G and 4G wireless application space, both baseband and Remote Radio Head (RRH) cards are required to handle multiple protocols as well as increased throughput in order to support higher cellular data rates while maintaining high Signal to Noise Ratio (SNR).

The LatticeECP3 DSP Solution

  • Up to 320 multipliers (18x18)
  • Enhanced 3rd Generation sysDSP Architecture
    • Dual-slice architecture
    • Fully cascadable blocks
    • Backwards compatible with ECP2M sysDSP block
  • Programmable Multipliers
    • Two 18x18, four 9x9 per slice
    • Single 36x36 across two adjacent slices for double precision / floating point
    • 18x36 MAC & 18x18 MMAC modes
  • 54-bit Cascadable ALU
    • Rounding & truncation
    • Neighboring ALU output chainable as third input for ternary adds
  • High performance modes
    • MULT (Multiplier)
    • MAC (Multiplier Accumulate)
    • MMAC (Multiplier Multiplier Accumulate)
    • MULTADDSUB (Multiplier Add/Subtract)
    • MULTADDSUBSUM (Multiply Add/Subtract and SUM)
    • SLICE (Fully-configurable sysDSP slice used for advanced functions)
    • Adder Tree
    • Wide Mux

White Paper - Embedded Signal Processing Capabilities of the LatticeECP3 sysDSP Block

Dual Slice Architecture

The LatticeECP3 sysDSP block consists of two identical slices to enable increased performance within the DSP block, provide finer control capability and to allow independent ALU operation.  Bypassable pipeline registers within each slice, allow the designer to remove propagation latencies.  The slices can also be chained with no routing penalties enabling wider multiplication and accumulator operations.
ECP3 - DSP dual slice

Cascadability

For many signal processing applications, where large FIR filters or FFTs are employed, it may be necessary to create large signal processing functions.  To accommodate this need, it is necessary to have DSP blocks cascaded together.  LatticeECP3 addresses the need for high performance signal processing functions, by connecting the accumulator output of one block directly to its adjacent DSP block input.
ECP3 - DSP - Cascadable