Optimized FPGA Architecture

LatticeECP3 FPGAs utilize Lattice’s third generation of transceivers and a cost-optimized 65-nm process FPGA architecture. Building on the successful LatticeECP2M FPGA family, LatticeECP3  devices deliver high performance SERDES blocks, cascadable high performance sysDSP, sysMEM embedded RAM, distributed memory, sysCLOCK PLLs, DLLs, DDR3 memory interface, and sysIO buffers, to provide a robust low-cost bridging solution for a wide range of applications.

Lattice ECP3 - Block Diagram

The following diagram provides an overview of the LatticeECP3 architecture. Additional details on all of the blocks can be found in the device datasheet.

Programmable Function Unit - Block Diagram

Each PFU block consists of four interconnected slices, each containing 2 LUTs numbered 0-3 as shown in the figure below

EBR (Mbits)

sysCLOCK PLL Block Diagram

The sysCLOCK PLLs provide the ability to synthesize clock frequencies.  The LatticeECP3 family support from 2 to 10 full-featured General Purpose PLLs.

sysMEM Config Options

The sysMEM block can implement single port, dual port, pseudo dual port or FIFO memories. Each block can be used in a variety of depths and widths as shown in the table below.