The LatticeECP3 family is the third generation high value FPGA from Lattice Semiconductor, which offers the industry's lowest power consumption and price of any SERDES-capable FPGA device. It offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs.
The entire LatticeECP3 family is manufactured using Fujitsu's advanced low power process technology.
Lattice has recently introduced three new classes of LatticeECP3 devices - Low Power, High Speed, and Mini FPGAs. The new devices allow designers to build emerging class of compact products capable of processing high-speed Video and Internet data. They bring high-end innovations such as configurable SERDES, cascadable DSP slices, high-speed DDR3 memory, and programmable fabric for designing portable professional and consumer products. The value added devices are ideal for power and space limited applications in professional cameras, surveillance cameras, medical imaging, video communication, and small form-factor wireline and wireless appliances. The LatticeECP3 Low Power FPGAs consume on the average 30% lower power compared to the LatticeECP3 standard devices and the High Speed FPGAs run 10% faster. The new additions also include industry’s tiniest FPGA with high-speed SERDES and DDR3 memory interface.
All three classes of devices have been fully qualified and released to volume production. They can be accessed for system design using the Lattice Diamond 1.4 Design Software. For more information on these new FPGAs, please visit the following pages:
Development Kits and Evaluation Boards are availableto help you evaluate the LatticeECP3 technology, or aid in the development of your own design. Each board includes example designs, schematics and other resources to help you accellerate the evaluation and development process.
| Device | ECP3-17 | ECP3-35 | ECP3-70 | ECP3-95 | ECP3-150 | |
|---|---|---|---|---|---|---|
| LUTs (K) | 17 | 33 | 67 | 92 | 149 | |
| EBR SRAM (Kbits) | 700 | 1327 | 4420 | 4420 | 6850 | |
| EBR SRAM Blocks | 38 | 72 | 240 | 240 | 372 | |
| Distributed RAM (Kbits) | 36 | 68 | 145 | 188 | 303 | |
| 18x18 Multipliers | 24 | 64 | 128 | 128 | 320 | |
| 3.2Gbps SERDES Channels | 4 | 4 | 12 | 12 | 16 | |
| Maximum Available I/O | 222 | 310 | 490 | 490 | 586 | |
| PLLs + DLLs | 2+2 | 4+2 | 10+2 | 10+2 | 10+2 | |
| Packages | SERDES I/O Combinations | |||||
| 328-ball csBGA (10 x 10 mm) | 2 / 116 |
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| 256-ball ftBGA (17 x 17 mm) | 4 / 133 |
4 / 133 |
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| 484-ball fpBGA (23 x 23 mm) | 4 / 222 |
4 / 295 |
4 / 295 |
4 / 295 |
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| 672-ball fpBGA (27 x 27 mm) | 4 / 310 |
8 / 380 |
8 / 380 |
8 / 380 |
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| 1156-ball fpBGA (35 x 35 mm) | 12 / 490 |
12 / 490 |
16 / 586 |
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© Lattice Semiconductor Corporation 2013
