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DSP Application Shape Continues To ExpandThe applications of Digital Signal Processing (DSP) continue to expand, driven by trends such as the increased use of video and still images and the demand for increasingly reconfigurable systems such as Software Defined Radio (SDR). Many of these applications combine the need for significant DSP processing with cost sensitivity, creating demand for high-performance, low-cost DSP solutions. FPGA and General Purpose DSP SolutionsTraditionally designers have utilized general-purpose DSP processors to implement DSP functions. General-purpose DSP chips combine efficient implementations of these functions with a general-purpose microprocessor. Typical clock speeds run from tens of MHz to 1GHz. Performance, as measured by Millions of Multiply Accumulates (MMAC) per second, typically ranges from 10 to 4000. Functions requiring higher performance have to be split across multiple DSP engines. The price of these chips ranges from a few dollars at the bottom end of the performance range to hundreds of dollars at the high end. A DSP oriented FPGA provides the ability to implement many functions in parallel on one chip. General-purpose routing, logic and memory resources are used to interconnect the functions, perform additional functions, sequence and, as necessary, store data. Some basic devices provide multiplier only support, requiring users to construct all other functions in logic. More sophisticated devices provide addition, subtraction and accumulator functions as part of their set of DSP building blocks. FPGAs typically have tens of multiplier elements and can operate at clock speeds of hundreds of MHz. For example, the LatticeECP2-70 has 88 multipliers that run at speeds of up to 325MHz, delivering performance up to 28,600 MMACs per second. The LatticeECP, LatticeECP2/M and LatticeXP2 DSP solution
The number of elements available in each block depends upon the width selected from the three available options: x9, x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP.
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The LatticeECP FPGA devices consist of a low-cost FPGA fabric coupled with between four and ten sysDSP blocks. The LatticeECP2/M devices provide between 3 and 42 sysDSP blocks. The LatticeXP2 devices provide between 3 and 8 sysDSP blocks in an Instant-On, Secure, Single Chip FPGA. The sysDSP block supports four functional elements in three data path widths: 9, 18 and 36. The resources in each sysDSP block can be configured to support the following four elements: 