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Lattice ispGDX2 Devices - 38 Gbps ISP Switch with Advanced System Features


Lattice ispGDX2 - 38 Gbps Bandwidth, 800 Mbps SERDES The ispGDX2 family is Lattice's next generation in-system programmable (ISP) high performance digital crosspoint switch for high-speed bus switching and interfacing with bandwidth of up to 38Gbps. This family combines a flexible switching architecture with advanced high speed serial I/O (sysHSI blocks), sysCLOCK PLLs, and sysIO interfaces to meet the needs of today's high-speed systems. A multiplexer based architecture and on chip control logic facilitate the high performance implementation of common switching functions. Devices in the family can operate at 3.3, 2.5 & 1.8V core Voltage.

The ispGDX2 family is available in two options. The standard device supports SYSHSI availability for ultra fast serial communications and the "E-Series", a high performance, low-cost device with no sysHSI functionality.

Family Member Selector Guide
Vcc Device Registers PLLs Duplex
SERDES
Channels*
Speed
tPDFmax
I/Os Packaging
1.8 ispGDX2/E-64C 64 2 4 3.0 360 64 100-fpBGA
ispGDX2/E-128C 128 2 8 3.2 330 128 208-fpBGA
ispGDX2/E-256C 256 4 16 3.5 300 256 484-fpBGA
2.5 ispGDX2/E-64B 64 2 4 3.0 360 64 100-fpBGA
ispGDX2/E-128B 128 2 8 3.2 330 128 208-fpBGA
ispGDX2/E-256B 256 4 16 3.5 300 256 484-fpBGA
3.3 ispGDX2/E-64V 64 2 4 3.0 360 64 100-fpBGA
ispGDX2/E-128V 128 2 8 3.2 330 128 208-fpBGA
ispGDX2/E-256V 256 4 16 3.5 300 256 484-fpBGA
* "E-Series" does not support sysHSI.

 

Features

High Performance Bus Switching

  • High Bandwidth
    • Up to 12.8 Gbps (SERDES)
    • Up to 38 Gbps (without SERDES)
  • Up to 16 (15X10) FIFOs for data buffering
  • High-speed Performance
    • fMAX = 360 MHz, tPD = 3.0ns
    • tCO = 2.9ns , tS = 2.0ns
  • I/O intensive: 64 to 256 I/Os
  • Expanded MUX capability up to 188:1 MUX

sysCLOCK PLL

  • Frequency synthesis and skew management
  • Clock shifting, multiply and divide capability
  • Clock shifting up to +/-2.35ns in 335ps steps
  • Up to four PLLs

sysIO Interfacing

  • LVCMOS 1.8, 2.5, 3.3 and LVTTL support
  • SSTL 2/3 Class I and II support
  • HSTL Class I, III and IV support
  • GTL+, PCI-X support
  • LVPECL, LVDS and Bus LVDS support
  • Hot socketing
  • Programmable drive strength
  • sysHSI Blocks provide up to 16 High Speed Channels
    • Serializer/de-serializer (SERDES) included
    • Built-in Clock Data Recovery (CDR)
    • 800 Mbps per channel
    • LVDS differential support
    • 10B/12B support
      • Encoding / decoding
      • Bit alignment
      • Symbol alignment
    • 8B/10B support
      • Bit alignment
      • Symbol alignment
    • Source synchronous capability
  • Two options available
    • High performance sysHSI (Standard part number)
    • Low-cost, no sysHSI ("E-Series" part number)

Flexible Programming & Testing

  • 1.8/2.5/3.3V Power Supply Options
  • JTAG Boundary Scan Test & ISP

Architecture

The diagrams below shows the major blocks of the ispGDX2-64 device.

Click diagrams to view enlargements.

ispGDX2-64 Top Level Diagram small
ispGDX2-64 Top Level Diagram
sysCLOCK PLL small
sysCLOCK PLL
 
sysHSI small
sysHSI
GDX Block small
GDX Block
 
sysIO small
sysIO
MRB Block small
MRB Block

 

Mature Devices

Click here for information on related older device families