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The ispGDX2 family is Lattice's next generation in-system programmable (ISP) high performance digital crosspoint switch for high-speed bus switching and interfacing with bandwidth of up to 38Gbps. This family combines a flexible switching architecture with advanced high speed serial I/O (sysHSI blocks), sysCLOCK PLLs, and sysIO interfaces to meet the needs of today's high-speed systems. A multiplexer based architecture and on chip control logic facilitate the high performance implementation of common switching functions. Devices in the family can operate at 3.3, 2.5 & 1.8V core Voltage.
The ispGDX2 family is available in two options. The standard device supports SYSHSI availability for ultra fast serial communications and the "E-Series", a high performance, low-cost device with no sysHSI functionality.
* "E-Series" does not support sysHSI.
Features
High Performance Bus Switching
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High Bandwidth
- Up to 12.8 Gbps (SERDES)
- Up to 38 Gbps (without SERDES)
- Up to 16 (15X10) FIFOs for data buffering
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High-speed Performance
- fMAX = 360 MHz, tPD = 3.0ns
- tCO = 2.9ns , tS = 2.0ns
- I/O intensive: 64 to 256 I/Os
- Expanded MUX capability up to 188:1 MUX
sysCLOCK PLL
- Frequency synthesis and skew management
- Clock shifting, multiply and divide capability
- Clock shifting up to +/-2.35ns in 335ps steps
- Up to four PLLs
sysIO Interfacing
- LVCMOS 1.8, 2.5, 3.3 and LVTTL support
- SSTL 2/3 Class I and II support
- HSTL Class I, III and IV support
- GTL+, PCI-X support
- LVPECL, LVDS and Bus LVDS support
- Hot socketing
- Programmable drive strength
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sysHSI Blocks provide up to 16 High Speed Channels
- Serializer/de-serializer (SERDES) included
- Built-in Clock Data Recovery (CDR)
- 800 Mbps per channel
- LVDS differential support
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10B/12B support
- Encoding / decoding
- Bit alignment
- Symbol alignment
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8B/10B support
- Bit alignment
- Symbol alignment
- Source synchronous capability
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Two options available
- High performance sysHSI (Standard part number)
- Low-cost, no sysHSI ("E-Series" part number)
Flexible Programming & Testing
- 1.8/2.5/3.3V Power Supply Options
- JTAG Boundary Scan Test & ISP
Architecture
The diagrams below shows the major blocks of the ispGDX2-64 device.
Click diagrams to view enlargements.
Click here for information on related older device families
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