Viterbi Decoder

Overview

Lattice's Viterbi Decoder is a parameterizable IP core with an efficient algorithm for decoding different combinations of convolutionally-encoded sequences. (Convolutional encoding is a process of adding redundancy to a signal stream in order to increase its robustness.) In the decoder, the convolutional coded sequences that have been corrupted by channel noise, are decoded back to the original sequence.

Many digital transmit-receive systems use a Viterbi decoder for decoding the convolutionally coded data. The digital data stream (e.g., voice, image or any packetized data) is first convolutionally encoded, modulated and transmitted through a wired or wireless channel. Noise from various sources is prone to enter into the channel. The data received from the channel at the receiver side is first demodulated and then decoded using the Viterbi decoder. By using both the original stream and the redundant stream, the Viterbi decoder core is able to correct for errors in the data caused by channel noise. The decoded output is equivalent to the transmitted digital data stream.

The decoder core supports various code rates, constraint lengths and generator polynomials. The core also supports soft-decision decoding and is capable of decoding punctured codes.

Features

• Parameterizable Viterbi decoder
• Available for ispXPGA and ORCA 4
• Single clock synchronous design
• Soft decision with parameterizable soft width
• Non-punctured code rates of 1/2 and 1/3
• Parallel or hybrid architecture implementation
• Parameterizable constraint length from 3 to 8
• Parameterizable convolution codes
• Parameterizable traceback length
• Internal depuncturing option
• Puncturing rates from 2/3 to 12/13
• Parameterizable puncture patterns for internal puncturing
• Bit error rate monitore

Evaluation Configurations

¹ Performance and utilization characteristics using ispLEVER^TM software and targeting the or4e04, package BM416, speed 2.
² Programmable Function Unit (PFU) is a standard logic block of Lattice devices. For more information, check the data sheet of the device.

¹ Performance and utilization characteristics using ispLEVER software and targeting the LFX1200B, package FE680, speed grade 4.
² Programmable Function Unit (PFU) is a standard logic block of Lattice devices. For more information, check the data sheet of the device.

Ordering Information

Part Numbers:
For ORCA 4: VTERB-DECO-O4-N1
For ispXPGA: VTERB-DECO-XP-N1
To find out how to purchase the Viterbi Decoder IP Core, please contact your local Lattice Sales Office.