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8-bit Microcontroller - LatticeMico8


LatticeMico8

Lattice Reference DesignsThe LatticeMico8 is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 32 General Purpose registers, the LatticeMico8 is a flexible reference design written in Verilog and VHDL suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.

The LatticeMico8 is licensed under a new open intellectual property (IP) core license, the first such license offered by any FPGA supplier. The main benefits of using open source IP are greater flexibility, improved portability, and no cost. This new agreement provides all the benefits of standard open source and allows users to mix proprietary designs with the open source core. Additionally, it allows for the distribution of designs in bitstream or FPGA format without accompanying it with a copy of the license.

Mico8 Block Diagram

Contribute to the LatticeMico8! Do you have designs you would like to share with us? Have you come across a bug? Is there a new feature you would like to see? Let us know! Send an email to Technical Support at techsupport@latticesemi.com.

Features

  • 8-bit Data Path
  • 18-bit Wide Instructions
  • Configurable 16 or 32 General Purpose Registers
  • Input/Output is Performed Using "Ports" (256 Ports/page, up to 65536 pages)
  • Optional 256 bytes of External Scratch Pad RAM
  • Two Cycles Per Instruction
  • Three cycles per Input/Output cycle (extendable using READY strobe)
  • Lattice UART Reference Design Peripheral

Evaluation Configurations

The following table shows a few of the many possible configurations. The v3.0 Mico8 core can be targeted to any Lattice FPGA.

Config. Number Description* Device LUTs Registers SLICEs f MAX (MHz)
1 16 - Regs, 32 byte Ext SP,
512 PROM, 8-bit Ext Address
LFXP3C-4,
LFEC3E-4
250 61 144 65.7 (LFXP3C-4)
78.8 (LFEC3E-4)
LCMX01200C-4 239 61 120 74.0 (LCMXO1200C-4)
LFE2-50E-5 265 61 155 103.5 (LFE2-50E-5)
2 32 - Regs, 32 byte Ext SP,
512 PROM, 8-bit Ext Address
LFXP3C-4,
LFEC3E-4
299 61 169 63.9 (LFXP3C-4)
71.7 (LFEC3E-4)
LCMXO1200C-4 290 61 145 77.0 (LCMXO1200C-4)
LFE2-50E-5 308 61 177 98.8 (LFE2-50E-5)
3 16 - Regs, 32 byte Ext SP,
512 PROM, 16-bit Ext Address
LFXP3C-4,
LFEC3E-4
255 69 145 66.7 (LFXP3C-4)
76.8 (LFEC3E-4)
LCMXO1200C-4 242 69 121 81.3 (LCMXO1200C-4)
LFE2-50E-5 274 70 157 102.6 (LFE2-50E-5)
4 32 - Regs, 32 byte Ext SP,
512 PROM, 16-bit Ext Address
LFXP3C-4,
LFEC3E-4
303 69 168 62.2 (LFXP3C-4)
66.5 (LFEC3E-4)
LCMXO1200C-4 296 69 148 72.5 (LCMXO1200C-4)
LFE2-50E-5 323 69 181 99.2 (LFE2-50E-5)

* SP = Scratch Pad

Documentation

PDF file LatticeMico8 User Guide


PDF file Technote 1095 - Using the LatticeMico8 Microcontroller with the LatticeXP Evaluation Board

 

Core Code

Version 3.0 of the LatticeMico8 increases addressable code space, has configurable address range and improved stack operations for support of high-level compilers, while keeping a very small footprint.  The code will run on ispLever 5.1 and later. The predefined ispLever project (i.e. .syn) files are valid for 7.0 and later.

EXE files LatticeMico8 Core Source Code Revision 3.0 Verilog - NEW


EXE files LatticeMico8 Core Source Code Revision 3.0 VHDL - NEW

 

Tool Code

EXE files LatticeMico8 Tools Code for Core Revision 3.0 and above
The above tools package contains both the source code and the executable files for the LatticeMico8

Demo

EXE files LatticeMico8 Demo

 

Useful External Links

Archived Code

EXE files LatticeMico8 Core Source Code Revision 2.4 Verilog
The above source code is the VHDL source code for ispLEVER version 6.0 and above.

EXE files LatticeMico8 Core Source Code Revision 2.4 VHDL
The above source code is the VHDL source code for ispLEVER version 6.0 and above.

EXE files LatticeMico8 Core Source Code Revision 2.3 Verilog
The above Verilog source code supports the LatticeECP2, the LatticeECP/EC, LatticeXP, and MachXO devices.  Additionally, this version handles a larger number of instructions (1024 for LatticeECP2) and supports a bigger jump/branch (2048). For new designs, it is recommended to use Revision 2.4.

EXE files LatticeMico8 Core Source Code Revision 2.3 VHDL
The above VHDL source code supports the LatticeECP2, the LatticeECP/EC, LatticeXP, and MachXO devices.  Additionally, this version handles a larger number of instructions (1024 for LatticeECP2) and supports a bigger jump/branch (2048). For new designs, it is recommended to use Revision 2.4.

EXE files LatticeMico8 Core Source Code Revision 2.2 Verilog Only
The above source code has a couple of bug fixes and has been fully tested for the MachXO family of Crossover Programmable Logic devices.

EXE files LatticeMico8 Core Source Code Revision 1.0 Verilog Only


EXE files LatticeMico8 Tools Code for Core Revision 2.3


EXE files LatticeMico8 Tools Code Revision 1.0