ispClock5312S Evaluation Board

The ispClock5312S Evaluation Board is a ready-made platform to help you evaluate and design with the ispClock5300 series of in-system-programmable zero delay universal fan-out buffers. The board includes an ispClock5312S in 48-pin TQFP package and a full set of features to help you use and evaluate the ispClock5312S. All user-programmable features of the ispClock5312S can be easily configured using Lattice Semiconductor's PAC-Designer® software.

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Product Contents

• ispClock5312S Evaluation Board Featuring:
• ispClock5312S in 48-pin TQFP package
• SMA connectors for access to selected high-speed I/O
• 8-bit configuration DIP switch
• Flexible on-board I/O termination
• Integrated power supply
• ispDOWNLOAD Cable
• AC Adapter
• User Documentation

Device Support

You will need the PAC-Designer software to use this board. PAC-Designer can be downloaded from the Lattice web site.

Ordering Information

Part Number: PACCLK5312S-EVN

To purchase this board, please visit our Online Store.