Note: This product is no longer available for purchase - it has been replaced by the new LatticeXP2 Brevia2 Development Kit. The The following information is provided for reference only.
The LatticeXP2 Brevia Development Kit is an easy-to-use, low-cost platform for evaluating and designing with LatticeXP2 FPGAs. The kit offers free design tools, reference designs, a small form-factor evaluation board, and a parallel programming cable. The evaluation board features a LFXP2-5E-6TN144C FPGA device, 2 Mbit SPI Flash, 1 Mbit SRAM memory, expansion headers, several LEDs, and user switches.
Using the preloaded Brevia system-on-chip (Brevia SoC) design provided with the development kit, you can now test within minutes SPI, UART and SRAM interfaces in addition to the 8-bit LatticeMico8 microcontroller. You can then build your own designs using the free downloadable source code for 28 reference designs, available in both VHDL and Verilog HDL formats. The easy-to-use Brevia Development Kit empowers designers to quickly build systems using readymade-blocks and implement them in less than an hour. The board also features parallel channels for JTAG programming and debugging from a host PC. The board can be controlled by a menu driven interface via terminal programs running on a host PC.
The Brevia Development Kit comes with a Lattice parallel port ispDOWNLOAD cable. If your PC does not have a parallel port connection (many new laptop PCs do not), you must purchase a Lattice USB ispDOWNLOAD cable, HW-USBN-2A. Please note that Lattice programming software does not operate with a 3rd party USB to parallel port adapter. Instead the USB ispDOWNLOAD Cable,HW-USBN-2A, should be used.
|LatticeXP2 Brevia Development Kit Documentation
Complete documentation including the Product Brochure, development kit QuickSTART guide, and User's Guide.
*** Special Note: The following demo application is native to the ispLEVER software. While you can continue to use ispLEVER if you have it installed, ispLEVER Starter is no longer available for download. Lattice Diamond-Free has replaced ispLEVER Starter, and should be used for all new design work. We are currently working to update this demo to work native to the Lattice Diamond environment, and will post a new version of the demo when available. Until that time, you can use the "ispLEVER project import" capability of Lattice Diamond. Depending on your needs, this may be a satisfactory interim solution.
A demo application, Brevia SoC, is included in the downloadable archive files. This demo includes the Verilog and VHDL source and firmware for the pre-programmed starter design provided with the LatticeXP2 Brevia Evaluation Board. It uses the 8-bit Microcontroller (LatticeMico8), SPI, and SRAM controller Reference Designs to build a complete system-on-chip, which communicates with a host PC via the serial RS-232 cable.
Please click a link on the right to download either Verilog or VHDL version of the source code and firmware for the demo.
|Diamond Software (Free License)
To modify a demo or create your own designs for the MachXO Control Evaluation Board download the Diamond Software. Access to design with the MachXO is included in the Diamond Free license, which you can request after you download and install the Diamond software. To program the MachXO Control Evaluation Board download ispVM System Device Programming Software.
|LatticeMico8 Reference Design & Development Tools
To modify the LatticeMico8 microcontroller firmware of the Brevia SoC demo requires the LatticeMico8 Tools Code Revision 3.0. You may download it from the link on the right.
LatticeMico32 Design Tools
Access a broad range of reference designs qualified for LatticeXP2 FPGA family. The reference designs can be downloaded from the web pages free of charge.
A comprehensive set of 28 new reference designs has been optimized for the LatticeXP2 FPGA family. These designs serve as a starting point for designers and cover a wide range of high-density applications. Each reference design includes a web page that provides a brief overview of the design, design documentation, and source code.
|Controller and Display||LatticeMico8 Microcontroller|
|LatticeMico8 to WISHBONE Interface Adapter|
|LCD Controller - WISHBONE Compatible|
|Serial Connectivity||SPI (Serial Parallel Interface) Controller - WISHBONE Compatible|
|UART (Universal Asynchronous Receiver / Transmitter)|
|UART (Universal Asynchronous Receiver / Transmitter) - WISHBONE Compatible|
|Control Link Serial Interface|
|HDLC (High-level Data Link Control) Controller|
|Bus Connectivity||PCI / WISHBONE Bridge|
|PCI to NOR Flash Interface|
|PCI Target 32-bit/33 MHz|
|LPC (Low Pin Count) Bus Controller|
|I2C (Inter-Integrated Circuit) Bus Master|
|I2C (Inter-Integrated Circuit) Slave/Peripheral|
|I2C (Inter-Integrated Circuit) Bus Controller for Serial EEPROMs|
|I2C (Inter-Integrated Circuit) Bus Controller with WISHBONE Interface|
|Arbitration and Switching between Bus Masters|
|Memory Controllers||SD Flash Memory Controller|
|NAND Flash Memory Controller|
|Compact Flash Memory Controller|
|SDRAM Controller - Advanced|
|Fast Page Mode DRAM Controller|
|System Control, Management, and Debug||Digital PWM Fan Controller|
|Power Manager-II Fault Logger|
|Simple Delta-Sigma ADC|
|GPIO / Interrupt Expander|
|BSCAN1 - Multiple Boundary Scan Port Addressable Buffer|
|BSCAN2 - Multiple Boundry Scan Port Linker|