ispClock5400D Evaluation Board

The ispClock5400D Evaluation Board includes everything the designer needs to quickly configure and evaluate the ispClock5406D in-system-programmable differential clock distribution device on a fully assembled printed-circuit board. The evaluation board can be used stand-alone to review the performance and in-system programmability of the 5400D device or as a companion board and clock source for LatticeECP3 FPGA evaluation boards:

The four-layer board supports a 48-pin QFNS package, a header for user I/O and a JTAG programming cable connector. SMA connectors are installed to provide high-signal integrity access to selected high-speed I/O signals. JTAG programming signals can be generated by using an ispDOWNLOAD® programming cable connected between the evaluation board and a PC. All user-programmable features of the ispPAC-CLK5406D can be easily configured using Lattice Semiconductor's PAC-Designer® software.

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Kit Contents

  • ispClock5406D Evaluation Board
  • ispDOWNLOAD Cable (HW-USBN-2A)
  • Universal AC Adapter
  • QuickSTART Guide

Board Photos

Top View

Click image to enlarge

Ordering Information

  • Ordering Part Number: PACCLK5406D-S-EVN
  • Click here to find an authorized Lattice distributor near you
  • Click here to order now from the Lattice Online Store

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock5400D Evaluation Board, QuickSTART
QS004 01.0 12/14/2009 PDF 1.6 MB
ispClock5400D Evaluation Board, User Guide
EB50 01.2 7/8/2010 PDF 2.3 MB
Programming Cable User Guide
Describes the features and recommended usage guidelines of Lattice ispDOWNLOAD Cables.
FPGA-UG-02042 26.4 5/29/2020 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock5400D Evaluation Board, Capture DSN
1.0 12/14/2009 ZIP 87.2 KB
ispClock5400D Evaluation Board, Gerber Artwork
1.0 12/14/2009 ZIP 357.8 KB
ispClock5400D Evaluation Board, Demo Source
1.0 12/14/2009 ZIP 0.7 KB

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