I2S Controller with WISHBONE Interface

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Reference Design LogoThe I2S bus (Inter-IC Sound bus) is a 3-wire, half-duplex serial link for connecting digital audio devices in an electronic system. The bus handles audio data and clocks separately to minimize jitter that may cause data distortion in the digital analog system. Invented by Philips Semiconductor, the I2S bus is widely used by equipment and IC manufacturers.

This reference design implements an I2S transmit master or I2S receive master with a WISHBONE interface.

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Block Diagram

Performance and Size

Implementation Results when the Design is Configured as an I2S Master Transmitter
Tested Devices* Language Performance I/O Pins Design Size Revision
LCMXO2-1200HC-4TG100CES Verilog > 50 MHz 55 241 LUTs 1.0
LCMXO2-1200HC-4TG100CES VHDL > 50 MHz 55 232 LUTs 1.0
LCMXO1200C-3T100C Verilog > 50 MHz 55 245 LUTs 1.0
LCMXO1200C-3T100C VHDL > 50 MHz 55 236 LUTs 1.0
Implementation Results when the Design is Configured as an I2S Master Reciever
Tested Devices* Language Performance I/O Pins Design Size Revision
LCMXO2-1200HC-4TG100CES Verilog > 50 MHz 55 298 LUTs 1.0
LCMXO2-1200HC-4TG100CES VHDL > 50 MHz 55 272 LUTs 1.0
LCMXO1200C-3T100C Verilog > 50 MHz 55 305 LUTs 1.0
LCMXO1200C-3T100C VHDL > 50 MHz 55 280 LUTs 1.0

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
I2S Controller with WISHBONE Interface Reference Design - Source Code
RD1101 1.1 3/1/2014 ZIP 1.6 MB
I2S Controller with WISHBONE Interface Reference Design Documentation
RD1101 1.1 3/1/2014 PDF 2.4 MB


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