I3C Master IP Core

Control for I3C Bus Interface

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I3C is a two-wire bi-directional serial bus, optimized for multiple sensor Slave Devices and controlled by only one I3C Master Device at a time. I3C is backward compatible with many Legacy I2C Devices, but I3C Devices also support significantly higher speeds, new communication Modes, and new Device roles, including an ability to change Device Roles over time (i.e., the initial Master can cooperatively pass the Mastership to another I3C Device on the Bus, if the requesting I3C Device supports Secondary Master feature).

Lattice I3C IP is intended to improve upon the features of the I2C interface, preserving backward compatibility. Implementing the I3C specification greatly increases the implementation flexibility for an ever-expanding sensor subsystem as efficiently and at as low cost as possible. Implementation follows the MIPI I3C specification to provide a single scalable, cost effective, power efficient protocol to solve issues with the high protocol overhead, increased power consumption, nonstandard protocol, separate lines for interrupt and the rest requirement. The MIPI I3C interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors.

Two main concerns are paramount for the I3C IP Core are the use of as little energy as possible in transporting data and control & reducing the number of physical pins used by the interface.

The I3C interface provides major efficiencies in bus power while providing greater than 10x speed improvements over I2C.


  • Two wire serial interface up to 12.5 MHz using Push-Pull
  • Legacy I2C Device co-existence on the same Bus (with some limitations)
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
  • I2C-like SDR and HDR-DDR messaging
  • Multi-Master capability
  • In-Band Interrupt and Hot-join support

Block Diagram

Ordering Information

Family Part Numbers Description
CrossLink-NX I3C-M-CNX-U Single-Design License
CrossLink-NX I3C-M-CNX-UT Multi-Site License


Quick Reference
I3C Master IP Core User Guide
FPGA-IPUG-02082 1.1 2/28/2020 PDF 2 MB

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