CLP-11 Tiny AES

Elliptic LogoNIST has standardized on a new cipher which can be implemented efficiently in hardware and software. It is becoming the cornerstone of cryptography and is now included in IPsec, 802.11i, 802.15 and 802.16 among many others. The advanced encryption standard (AES) block from Elliptic is fully proven in silicon and now shipping in volume. The CLP-11 is a high performance cipher block that performs encryption, decryption and key expansion in a very small silicon area – perfect for applications where cost is paramount.

The Advanced Encryption Standard (AES) algorithm is a subset of the Rijndael algorithm. It was selected by NIST as a replacement algorithm for DES which is no longer considered cryptographically secure due to the susceptibility of brute force attacks using modern computational power. The AES algorithm is a 128 bit block cipher and supports three different key sizes; 128, 192, and 256 bits.

The CLP-11 implementation fully supports the AES algorithm for all key sizes. The goal of the design was to create a design in a very small silicon footprint which is suitable for throughput in the 1 Mbps to 40 Mbps range. Unlike other small gate count cores, the CLP-11 implements the complete cipher operation including key expansion, encryption and decryption. The CLP-11 uses the base cipher mode AES-ECB (Electronic Code Book). The core can be wrapped with additional logic to support any other AES modes such as CBC, OFB, CRB, CTR, CCM, etc.

The core operates in one of three modes:

  • Key update - pass the key then expands the key for a cipher operation
  • Encrypt plaintext at the input to ciphertext at the output
  • Decrypt ciphertext at the input to plaintext at the output

Features

  • Electronic Code Book algorithm
  • Optional support for CBC mode if required
  • 32 bit data and control bus interface
  • Support for 128, 196 and 256 bit keys
  • Automatic generation of key context from key data
  • Core verified through NIST FIPS vectors ensure complete standards compliance

Jump to

Block Diagram

Performance and Size

Device Speed grade SLICEs Fmax Throughout
ECP -5 1917 33 MHz 16 Mbps1
XP -5 2995 58 MHz 29 Mbps1

1 Throughput stated for 128 bit keys

Ordering Information

This IP core is supported and sold by Elliptic Tech, contact Elliptic Tech at info@elliptictech.com or visit their website at www.elliptictech.com for more information.

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