Power Sequencing with Fault Logging Demo

Using ASC Bridge Board with MachXO3-9400 Development Board and ASC Breakout Boards

System wide control of DC/DCs and resets – This demo shows 31 pseudo DC/DC enables and/or reset signals sequenced from a central control point.

Fault logging with timestamp – Over and under voltage faults are recorded in non-volatile memory with a 32 bit timestamp.

Scalable architecture – This demo illustrates how adding L-ASC10s to a design can expand system management while maintain a central point of control.

Features

  • Four separate Power Planes are monitored and sequenced from a central control point
  • Over or under voltage faults are stored in user flash memory (UFM)
  • Fault logs include a timestamp of 32 bits with one second resolution
  • Fault logs can be read and cleared
  • Individual Power Planes can be sequenced down – replaced – and sequenced up
ASC Bridge Board with MachXO3-9400 Development Board and ASC Breakout Boards

Jump to

Block Diagram

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Power Sequencing with Fault Logging Demo using ASC Bridge Board User Guide
FPGA-UG-02079 1.0 11/30/2018 PDF 2.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Power Sequencing with Fault Logging Demo using ASC Bridge Board Demo
1.0 9/1/2018 ZIP 124 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Platform Manager 2 I2C GUI
1.1 10/7/2014 ZIP 3.3 MB


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