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PAC-Designer Software

In Detail
Documents & Downloads
See Also

PAC-Designer is a complete design and verification solution supporting power management and programmable clock device families. It is comprised of the downloadable modules shown below, including Aldec's Active-HDL Lattice Web Edition (LWE) HDL simulator. These downloadable software components, when coupled with ispVM System, support complete design from concept to programming.

PAC-Designer is supported on the Windows Vista (32-bit), Windows XP, Windows 2000 and Windows NT 4.0 operating systems.

The PAC-Designer 5.2 software was updated on 9-Nov-2009.

Follow the steps below to Download, Install, and License PAC-Designer.


Step One		    

Download PAC-Designer

Before you begin download and install, log-in or request a Lattice web site account. To download software from the Lattice Semiconductor web site, you must have an account. If you don't have an account, you will be prompted to create one.

PAC-Designer is organized into modular components. Refer to the table below to select the appropriate modules for the design environment you wish to build.

 
PAC-Designer Modules
Module Device Support / Feature Download

Primary Module: This is a required module to run the PAC-Designer software. It includes the Schematic View, LogiBuilder, compiler, and all the tools and device libraries you need to implement a design in Lattice's newest and most popular power management and programmable clock products.

Power Management
ProcessorPM
POWR607
POWR1014/A
POWR1220AT8
POWR6AT6
POWR604
POWR1208
POWR1208P1

Programmable Clock
ispClock5300S
ispClock5400D
ispClock5600A

 Primary Module (.exe 31MB)

Aldec Active-HDL Lattice Web Edition (LWE) Module (Optional): To simulate the HDL files exported by PAC-Designer, download this optional module that adds the Active-HDL LWE Verilog HDL and VHDL simulation environment from Aldec.

 HDL simulator Aldec Active-HDL LWE (.exe 334MB)

Step Two		    

Install each PAC-Designer Module

Starting with the Primary Module, double-click the downloaded file(s), to start the installation procedure.

Perform the following steps to install the PAC-Designer Primary Module:

  1. Running the self-extracting executable file (pacd52_install.exe) will automatically begin the setup and installation of the PAC-Designer software into a user-designated directory (The default directory is c:PAC-Designer52).
  2. When prompted by the installation setup program, select to add these files to the existing installation path.
  3. Reboot your PC before running the software (After setting the environment variables in your autoexec.bat file or control panel, system, you must reboot your PC).

Your PAC-Designer software installation is now complete. 

Perform the following to install the optional Active-HDL Module:

  1. Running the self-extracting executable file (Active-HDL_<ver>_Lattice_Web_Edition_<date>.exe) will automatically begin the setup and installation of the Active-HDL software into a user-designated directory (The default directory is c:Active-HDL Lattice Web Edition).

Your Active-HDL Lattice Web Edition software installation is now complete. 

Step Three		    

License Active-HDL Lattice Web Edition (LWE) Simulator (Optional)

Request an ispLEVER-Starter or ispLEVER-Classic license. Active-HDL LWE requires a valid ispLEVER-Starter/Classic software license. License files are supplied by Lattice via email. Save the resulting license.dat file to <install_path>/License. Once licensed, Active-HDL LWE is ready to run.

 

Features

  • Fully integrated design and simulation environment for Power Manager II, and ispClock devices
  • High level logic design mechanism
  • Easy-to-use GUI

Design Entry

  • Hierarchical design entry
    • Pulldown menu for selecting clock signaling specification
    • Simple navigation mechanism for configuring analog & digital functional blocks
    • Schematic entry for internal connections and setting parametric circuit values
  • High level design entry for flexible power management
    • LogiBuilder
  • Design utilities
    • I2C utility
    • Trim margin utility
    • Clock frequency synthesis
    • Graphical skew editing
    • Frequency calculators

Simulation

  • Export VHDL or Verilog HDL models to popular 3rd party HDL simulators New!
  • Create your power management stimulus graphically
  • Digital waveform simulation for easy design verification
  • Simulate power supply rate

 

Programming

  • Use PAC-Designer to download your designs to silicon via a Lattice ispDOWNLOAD Cable.
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Screenshots

Hierarchical Design Entry to Configure ispPAC-POWR1208's Analog & Digital Interface - click to enlarge

Hierarchical Design Entry to Configure
ispPAC - POWR1014/A &
ispPAC-POWR1220AT8's Analog &
Digital Interface
ispClock5410D with PAC-Designer Design Entry

ispClock5410D Design Entry
LogiBuilder Screen For Flexible Power Supply Sequencing and Monitoring - click to enlarge

LogiBuilder Screen For Flexible Power
Supply Sequencing and Monitoring
Frequency Synthesizer - click to enlarge

Frequency Synthesizer
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Minimum System Requirements

  • Pentium Compatible PC
  • 128 MB of RAM (256 MB highly recommended)
  • PAC-Designer: 70 MB free hard disk space
  • Active-HDL LWE: 850 MB free hard disk space
  • Mouse and mouse driver
  • Windows Vista, XP or NT/2000
  • IE version 5.X or later
  • Parallel or USB port for an ispDOWNLOAD cable
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