LatticeMico System What's New

LatticeMico System for Diamond 1.4

The following enhancements have been made:

• The LatticeMico8 Microcontroller (v3.3) was updated as follows:
  • The Carry and Zero flags are correctly saved and restored on interrupt entry and exit events respectively,
  • The interrupt handler ASM has been fixed to remove interrupt stack corruption when stack pointer reaches page boundary, and
  • The core comes out of reset gracefully when a reset even occurs during an ongoing WISHBONE bus access.
• SDRAM Controller (v3.2) was updated to resolve a synthesis issue.
• Slave Passthrough (v3.2) had support added to LatticeMico32 and LatticeMico8 drivers that enable user-defined interrupt handling.
• GPIO (v3.4) was updated to address an issue with synthesis when the component is configured for both input and output ports and the widths of each are different.
   

LatticeMico System for Diamond 1.3

Below is the list of enhancements:

• A Memory Passthrough component (v3.0) has been added, which provides a data path between the LatticeMico internal WISHBONE bus and the external WISHBONE memory devices
• An option has been added to the LatticeMico32 Microprocessor (v3.8) to dynamically change the exception base address (EBA) to a debug stub by asserting an LM32 GPIO pin named at debug. This pin is exposed to the design only when this option is enabled.
• Support for Wishbone ERROR signal in the LatticeMico32 Microprocessor (v3.8) has been added. The WISHBONE interconnect will assert the WISHBONE ERROR signal when an access is made to an undefined address. LatticeMico32 will translate this ERROR signal into Data or Instruction Abort if the access originated from LatticeMico32's Data or Instruction WISHBONE ports respectively.
• The DDR3 controller IP core version 1.3 can be used as a peripheral of LatticeMico32 

LatticeMico System for Diamond 1.2

LatticeMico32 System  is renamed LatticeMico System

LatticeMico32 System has been renamed LatticeMico System, as it now supports both LatticeMico32 (32-bit microprocessor) and LatticeMico8 (8-bit microcontroller).

LatticeMico System now supports LatticeMico8 too.

LatticeMico System has been updated to include LatticeMico8 version 3.2. This new architecture of LatticeMico8 has been qualified for the MachXO2 device family. 

It can also be used to target other devices as a reference design.

Below is the list of peripheral components that LatticeMico System provides along with the two processors:

(*) The DDR3 controller IP core version 1.3 has been added as a peripheral of LatticeMico32

Component Updates with LatticeMico System 1.2

The tools provide support for building hardware platforms with multiple instances of the Lattice Tri-Speed Ethernet Media Access Controller (TSMAC) IP core version 3.4 onwards

Changes have been implemented in the following components:

• LatticeMico32 microprocessor v3.7
• On-Chip Memory v3.4
• Parallel Flash controller v3.1
• Async SRAM controller v3.1
• SPI Flash v3.4
• DMA v3.3
• UART v3.6
• GPIO v3.3

If the user chooses to update, the new components will be incorporated when the platform is regenerated, otherwise the platform will contain the current components.

LatticeMico System prior to release1.2

Migrating from LatticeMico32 Platforms prior to Lattice Diamond 1.1 (or ispLEVER 8.1 SP1)

LatticeMico32 Platform generation has been enhanced to accommodate 8 and 16 bit bus masters as well as 32 bit bus master already supported. This required making updates to some components. A platform that was generated from Mico System Builder prior to Diamond 1.1 or ispLEVER 8.1SP1 and uses one of these components may require some modification to the software or platform wrapper if it is re-generated in Lattice Diamond 1.1 or ispLEVER 8.1SP1 or later versions with these updated components.

See the technote TN1221 for a complete discussion of the changes made, whether they impact your specific platform, and how to migrate your platform for use with Lattice Diamond 1.1 or ispLEVER 8.1SP1 or later.

The components that were updated with Lattice Diamond 1.1 are:

• DMA (v3.1)
• GPIO (v3.1)
• SPI Flash (v3.2)
• UART (v3.4)