ispLEVER 7.0 SP1 and SP2 - PLL Connectivity Updates

Two database updates for PLL connectivity for the LatticeECP2 and LatticeECP2M FPGA families are available for users of ispLEVER 7.0 + Service Pack 1 (SP1) and/or Service Pack 2 (SP2). Please read below for more information on these updates.

You must install ispLEVER 7.0 SP1 prior to installing these updates.

If you have already installed these updates with ispLEVER 7.0 SP1, and subsequently install SP2, you do not need to re-install these updates.

To download the update files, click on the "Downloadable Software" link at the left of this page.

LatticeECP2 Update

Purpose

This is an update to PLL routing connectivity for all members of the LatticeECP2 device family.

Who should get this update

Users wanting to utilize Dynamic Clock Switching (DCS) between two CLKOK signals from two different PLL’s on the same side of a device or when more than 6 primary clocks are used in a design.

Design considerations if you choose not to update

Ensure the PLL’s used are not on the same side of the chip when switching between two CLKOK signals or use different PLL outputs, such as CLKOS or CLKOP.

LatticeECP2M Update

Purpose

This is an update to PLL routing connectivity for the LatticeECP2M-50, ECP2M-70, and ECP2M-100 devices.

Who should get this update

Any design using the uppermost right and/or uppermost left PLLs in any of these devices.