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ispLEVER Classic is the design environment for Lattice CPLDs and mature programmable products. It can be used to take a Lattice device design completely through the design process, from concept to device JEDEC or Bitstream programming file output. Details about the programmable logic families supported with ispLEVER Classic are below.
The current version is ispLEVER Classic 1.3, released on August 3rd, 2009
ispLEVER Classic download is supported on the Windows Vista (32-bit), Windows XP or Windows 2000 operating systems. A Linux compatible version of ispLEVER Classic is included with ispLEVER Linux (LS-ADV-LX-F). Note: MACH 5 and ispLSI1000/2000/5000 devices are not supported on Linux OS.
To design with other Lattice FPGA families, download the ispLEVER Starter software. You can install and run both ispLEVER Starter and ispLEVER Classic concurrently.
Downloading and installing ispLEVER Classic
Follow the three steps below to pick Download, Install, and License ispLEVER Classic.
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Download
ispLEVER Classic consists of four modules as listed below; The ispLEVER Classic 1.3 Base Module installation, the ispLEVER Classic 1.3 FPGA Module installation, Synplify Synthesis Module, and the Aldec Active-HDL Lattice Web Edition, which adds simulation capability.
Click the links below to download these modules.
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ispLEVER Classic Modules
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Device Support / Feature |
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ispLEVER Classic 1.3 Base Module: This includes the ispLEVER Project Navigator, and all the tools and device libraries you need to implement a design for any of the programmable families listed at the right.
These devices are supported by the Lattice gate-level logic simulator supporting ABEL/Schematic, VHDL, Verilog, and HDL/Schematic designs. For more advanced simulation capabilities, download the Aldec Active-HDL Lattice Web Edition simulator below.
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CPLD
ispMACH 4000B/C/V/Z/ZE
ispMACH 5000VG
ispMACH 5000B
ispMACH 4A3/5
MACH4/5
ispXPLD 5000MX
ispLSI 8000
ispLSI 5000VE
ispLSI 2000VE
ispLSI 1000
SPLD
GAL and ispGAL
GDX
ispGDXVA
ispGDX2
FPGA
ispXPGA
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ispLEVER Classic Base Module (.exe 323 MB) |
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ispLEVER Classic 1.3 FPGA Module: This optional module adds support for ORCA FPGA and FPSC devices.
Note that the Base Module must be installed prior to the FPGA Module.
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FPGA
ORCA FPGA
ORCA FPSC |
ispLEVER Classic FPGA Module (.exe 394 MB) |
| Synplify Synthesis Module: This optional module that includes the Lattice version of the Synplify™ synthesis tool from Synplicity®. This allows you to target and synthesize your HDL designs for Lattice CPLD and FPGA products. Supported HDL languages include; VHDL, Verilog 1995, Verilog 2001. |
HDL synthesis
Version: 9.4 L1 |
Synplify Synthesis Module Request Form
Click the link above to request a download. You will be sent a download link via e-mail. This procedure is required to comply with US export regulations. |
Aldec Active-HDL Lattice Web Edition (LWE) Module: This optional module adds simulation capability from Aldec.
Important: Do not install this module if you have already installed ispLEVER 7.2, ispLEVER PRO 7.2 or later. See the Active-HDL Lattice Edition Libraries for CPLD, SPLD, and Mature FPGAs page for details.
The default installation of Active-HDL LWE is a stand-alone product. If you wish to run Active-HDL directly from the ispLEVER Project Navigator, select Options->Environment... from the main Project Navigator menu. Click on the "Directories" tab, and in the "Active-HDL" field, enter the Active-HDL installation path + "bin" directory (i.e. <install path>/bin)
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Simulation
Version: 8.1 (Lattice Web Edition) |
Aldec Active-HDL LWE Simulation Module (.exe 314 MB) |
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Install each ispLEVER Classic Module
Starting with the ispLEVER Classic Installation, double-click the downloaded file(s), to start the installation procedure.
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License ispLEVER Classic
ispLEVER Classic requires a valid software license. To obtain a license go to our licensing page to request a 1-year term license. License files are supplied by Lattice via email. Save the resulting license.dat file to <install_path>License. Once licensed, ispLEVER Classic is ready to run.
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