What’s New in ispLEVER

ispLEVER® 7.1 is the latest FPGA design software from Lattice Semiconductor. With a full set of advanced tools to improve your productivity and design performance, ispLEVER is better and easier-to-use than ever before.

ispLEVER for Windows, UNIX and Linux features the industry-leading Synplify® Pro VHDL and Verilog synthesis tool from Synplicity®, including tools like HDL Analyst for powerful Verilog and VHDL view/debug. ispLEVER for Windows also includes the very high performance Aldec Active-HDL Lattice Edition timing and functional simulator, which provides 2-3 times faster simulation (compared to previous versions) and mixed language support.

This web page provides an overview of what’s new in ispLEVER 7.1 (as well as previous releases). For complete details on all software enhancements, along with hyperlinks to the related help topics, open the “What’s New?” topic in the ispLEVER software help.

To see ispLEVER Known Issues and Workarounds, please visit the new Lattice Forums pages and search for  “ispLEVER 7.1 Known Issues”.

Synplify Pro for Lattice

ispLEVER 7.1 now includes Synplify Pro for Lattice. This valuable addition to ispLEVER includes a range of tools and features that help you manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs.

Synplify Pro for Lattice - New in ispLEVER 7.1

Additional key features of Synplify Pro for Lattice not previously included with ispLEVER, include:

• HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code.
• Mixed VHDL and Verilog synthesis support
• Automatic re-timing (balancing registers across combinatorial logic) for improved performance
• Automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA.
• Windows, UNIX and Linux platform support.

Aldec Active-HDL Lattice Edition

ispLEVER 7.1 now includes the most comprehensive and feature-rich simulation environment available – Active-HDL Lattice Edition (LE) from Aldec.

Aldec Active-HDL Lattice Edition - New in ispLEVER 7.1

You’ll now have access to simulation capabilities and features never before available with ispLEVER. Active-HDL LE is also dramatically faster for large designs than previous solutions. Important features of Active-HDL LE include:

• Mixed language simulation support (VHDL and Verilog or SystemVerilog and Verilog)
• Testbench generation from waveforms
• Design Flow Manager
• Workspace and design archiving
• Simulate Synplicity-encrypted IP (VHDL and Verilog)
• SystemVerilog IEEE 1800 design
• Memory viewer

New Design Planner Features & Tools

The ispLEVER Design Planner is greatly improved with ispLEVER 7.1, including new capabilities like the SSO Analyzer - unique to Lattice. New features of the Design Planner include:

• SSO Analyzer: Simultaneous switching output (SSO) analysis describes the noise caused by a large number of output drivers switching at the same time. Lattice has invented a new tool – the SSO Analyzer – which applies the I/O configuration and PC board-level noise to estimate ground bounce and voltage drop conditions. Results are presented in a navigable HTML report and annotated onto the graphical Package View of the Design Planner tool.
• Timing Analyzer View: Run setup or hold analysis and cross-probe the timing paths in Floorplan View.
• Enhanced Dialog Box Filters with Wildcard Support: Allow you to specify multiple elements to be included in a single preference.
• “HDL Export Attributes” Command: Export UGROUP and REGION preferences to an HDL file.
• And Much More: Interactive Trace Report, Enhanced EBR and DSP Block Information, Color Coded Port Groups and DQS Span, Improved Pin Display Select Dialog, Distinct Automatic versus User Assignments, Preprocessor Directives for LPF Preference Files.

ispLEVER Classic 

Released in conjunction with ispLEVER 7.1, ispLEVER Classic 1.1 supports the new ispMACH® 4000ZE, the lowest-power CPLD ever available. With standby current as low as 10μA typical, and advanced features like Power Guard, per-pin pull-up/down, bus keeper control and performance to 260MHz, the ispMACH 4000ZE is the ideal solution for today’s power-sensitive portable applications.

ispLEVER Classic is the design environment for Lattice CPLDs and mature FPGAs.

Performance Improvements

ispLEVER 7.1 has been optimized to bring an average 5% improvement to the top operating frequencies
of designs, and as much as a 30% reduction in the time it takes to process larger designs, compared to previous ispLEVER releases.

ActiveSupport

A new optional feature that reports statistical information about how ispLEVER, IP, and FPGA resources are used to help us improve future products.

EPIC Device Editor

• Added a wildcard filter in the Signal Probing Configuration dialog for signal searching.
  
• Enhanced the signal probing process; you can save a signal probing list and reuse it later.

ispLeverDSP MATLAB/Simulink (Windows only)

LatticeMico32 System (Windows & Linux)

• LatticeMico32 Debugger can be run simultaneously with the other on-chip debugging tools.
  
• Static branch predictor predicts the outcome of conditional branches and prefetches instructions at the predicted target address.
  
• The LatticeMico32 UART component now features configurable FIFOs.
  

Memory Generation Tool

• Displays a default memory initialization file when MemGen starts.
  
• Saves the Data Radix and Address Radix settings to memory initialization (.mem) file.
  

Power Calculator

• New graphs to vary the voltage, temperature, and clock frequency.
  
• New I/O Termination tab.
  
• New fields added to the I/O tab for bidirectional signals, including a duty cycle field.

Project Navigator

• The Verific HDL parser analyzes the entire design to check syntax and create design hierarchy.
  
• New multi-tab Sources window & search bar.
  
• A new User-Defined File List to define the correct file order and exclude input files for synthesis and simulation.
  
• The new Module/IP Creation option in the New Source dialog box now lists Module Definition as a new source type.
  
• Improved TRACE engine makes placement and routing faster and uses less memory.
  
• The new interactive synthesis design flow works partly in the synthesis tool’s environment.
  
• Guided mapping and guided place & route flows allow you to guide mapping or placement/routing of a design after minor changes are made.
  
• Two new PAR explorer options have been added to help improve performance in designs with multiple congestion hot-spots.
  
• Over 30 new processes and properties have been added to the Project Navigator.
  

Reveal Inserter and Logic Analyzer

• Reveal Logic Analyzer can be run simultaneously with other on-chip debugging tools.
• Integer types, Boolean types, and user-defined enumerated types are now supported in VHDL in the RTL flow.
• New Timestamp option in the Trace Signal Setup tab enables you to count the relative time the sample was captured.
• Supports multiple token radixes so that you can use different radixes for different buses in Reveal Logic Analyzer.
  
• Specify whether the output trigger signal from outside the core is active high/low.
  
• Specify the pulse width of the trigger out signal.
  

Schematic Editor

• Updated and expanded Schematic Library
• New net and symbol attributes include new controls for LatticeSC™ I/O library elements, and SLICE/LUT-level controls like INIT, COMP, and LOC.
  

Previous Release Summary