This web page provides an overview of what’s new in ispLEVER - both the most recent release, as well as previous releases. For complete details on all software enhancements refer to the ispLEVER software help.
ispLEVER® 8.0 is now available. This software release includes a major update to the support of the LatticeECP3 FPGA family as well as powerful enhancements to the LatticeMico32 based solution. An updated version of Synopsys® Synplify Pro® for Lattice (C-2009.03L-1) and Aldec® Active-HDL™ Lattice Edition (8.2) are included in 8.0.
Note: Migrating existing LatticeECP3 designs to ispLEVER 8.0 requires understanding the changes in the software for LatticeECP3 support. For more information please refer to the ispLEVER 8.0 Release Notes for LatticeECP3 Migration.
New Software Features
Updated support of LatticeECP3 family for Generic DDR interfaces
Additional supported generic DDR interfaces allows more implementation choices, including in some cases, the support of more interfaces per device
HDL Generation from IPexpress™ GUI tool of the user defined generic DDR interface configuration (DDR_GENERIC). Among the many benefits:
Chooses the most appropriate interface based on requirements such as number of interfaces, interface width and speed
Avoids errors from hand coding complex interfaces
Allows much more convenient use of the DQS grouping structure for pins which aids pin layout work.
Enhanced support of the LatticeECP3 EA devices. This release allows access to additional capability that EA devices have for generic DDR interfaces.
Enhanced static timing analysis of generic DDR interfaces. The clock domain crossing analysis within generic DDR is now automatically included in Trace’s new Timing Rule Check section. User does not need to add explicit timing constraints for this analysis
Updated support of LatticeECP3 family for DDR Memory Interfaces
Enhanced DDR memory interface HDL generation from IPexpress GUI tool. Now capable of building the complete I/O-specific circuitry for proprietary DDR memory interfaces, allowing designers to focus solely on the controller logic of their DDR1 and DDR2 DRAM interfaces.
Improved Quality of Results vs. ispLEVER 7.2SP2
30% faster runtime to place and route large, congested designs, in addition to improved routability.
IPexpress
In addition to the numerous enhancements for Generic DDR and DDR Memory interface generation, IPexpress also contains improvements to other modules. The PCS module has been enhanced so Trace analysis will automatically be done on clocks originating from the PCS block (no need for user to set these FREQUENCY preferences).
ispLeverDSP MATLAB/Simulink
(Available only in the Windows version.) A new block, the Lattice Cascaded Integrator-Comb (CIC) Filter IP core, is now available in ispLeverDSP blockset. See DSP Guide for FPGAs for detailed description.
Added support for The Mathworks® MATLAB/Simulink R2009a
ispVM System
The ispVM® System software has been upgraded to version 17.6. New features and enhancements include:
The Monitor Download Cable Connection command in the Options menu. Enabling this command allows the software to check download cable connection and indicate the change when the cable is disconnected or the board power is turned off.
Added support for Lattice FTDI USB2 download cable. To use the cable, you must install the FTDI Windows USB driver. See Installing/Uninstalling Parallel Port Driver and USB Driver in the ispVM System Help.
Improved automatic cable detection. You can now use Auto Detect to list all the cables connected to your computer and then select one from the list. See Using Auto Detection in the ispVM System Help for more information.
LatticeMico32 Solution Enhancements (Available only in the Windows and Linux versions)
New Dual-Port On-Chip Memory Controller component
New UART feature, emulating C/C++ "printf"
New SPI Flash Controller with read/write support (replacing the SPI Flash ROM with read-only support)
Tri-Speed MAC (TSMAC) IP upgraded to enable higher system throughput. Now has dual WISHBONE Slave Ports and Burst Read/Write Support for RX/TX FIFOs
LatticeMico32 GNU Compiler upgraded to Version 4.3.0 for software performance improvement
Tutorial updated to target LatticeECP2
Addition of Synplify Pro to ispLEVER Starter Edition
Previous to v8.0 of ispLEVER Starter, the synthesis tool included was Synplify. Now, Synplify Pro will be also included. Users who have been using Synplify are strongly encouraged to start using Synplify Pro as Synplify will be removed from future releases of ispLEVER Starter.
Linux support has been upgraded to Red Hat Enterprise Linux (RHEL) 5.3. Note that ispLEVER, ispVM, and LatticeMico32 System run as 32 bit applications when run on a 64 bit OS. ispLEVER 8.0 for Linux now supports the following versions:
ispLEVER 8.0 includes Synplify Pro release C-2009.03L-1 which provides beta support of compile points for Lattice EC, ECP, ECP2/M, ECP3, MachXO, SC/M, XP, and XP2. This beta level support has been included with the intent to allow users to become familiar with using compile points for incremental synthesis. More information on this feature is available in the Synplify Pro release notes and user guide.
Synplify Pro for Lattice
Additional key features of Synplify Pro for Lattice include:
HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code.
Mixed VHDL and Verilog synthesis support
Automatic re-timing (balancing registers across combinatorial logic) for improved performance
Automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA.
Windows, UNIX and Linux platform support.
Aldec Active-HDL Lattice Edition
ispLEVER 8.0 includes version 8.2 of Active-HDL Lattice Edition (LE) from Aldec.
Aldec Active-HDL Lattice Edition
Important features of Active-HDL LE include:
Mixed language simulation support (VHDL and Verilog or SystemVerilog and Verilog)
Testbench generation from waveforms
Design Flow Manager
Workspace and design archiving
Simulate Synplicity-encrypted IP (VHDL and Verilog)
SystemVerilog IEEE 1800 design
Memory viewer
More information is available in the Aldec-HDL LE Tutorial - included in the ispLEVER help.
Previous Release Summary
Version
New features
7.2 (plus SP1-2)
(December 2008 - June 2009)
New Device Support
LatticeECP3 70E, ECP3-95E, and 150EA devices
LatticeXP2 BGA and QFP packaging
MachXO caBGA256 package
Software Features
New PAR technology that can reduce runtime as much as 30%.
Lattice “clock boosting” support for the Lattice ECP2/M families.
Timing Analyzer view improvements to more quickly visualize your critical timing paths.
The Clock Domain Analysis Report added to the Trace static timing analysis report.
Project Navigator added user control of file scan and syntax check of source file list
IPExpress improvements for Block Memory (EBR-based) and dual clock FIFO (FIFO_DC)
Design Planner interactive trace report and improved region floorplanning
New MAP global control for I/O registering
Trace improvements for increased accuracy
Improved Power Calculator accuracy for IO power consumption
ORCAstra onchip configuration tool support now extended to XP2
Greater ease of use and user control of Global Set Reset resource
ispLeverDSP support of MATLAB 2008a
New Reveal triggering options and support for MachXO and ECP3
Updated Synplify Pro for Lattice
Updated Aldec Active-HDL Lattice Edition
7.1 (plus SP1)
(May - September 2008)
New Device Support
LatticeXP2 (full production support)
ispMACH® 4000ZE (via ispLEVER Classic 1.1)
Software Features
Synplify Pro for Lattice
Aldec Active-HDL Lattice Edition
Performance improvements
Industry’s first SSO Analyzer
Design Planner: Timing Analyzer View, Wildcard support, and much more
Improved Trace engine makes placement and routing faster and use less memory
New integrated synthesis design flow works partly in the synthesis tool’s environment
LatticeMico32 System tools updated
New OS support (Windows®: Vista (32-bit), Linux: Novell SUSE® Enterprise v.10 SP1
7.0 (plus SP1-2)
(June - December 2007)
New Device Support
LatticeXP2
Software Features
Significant performance improvements
Reveal Logic Analyzer
New Power Calculator & improvements
Mixed-language design expanded
Numerous new features in the Design Planner
New IPexpress modules and options
New ispLeverCORE™ IP modules
LatticeMico32 System updated
PCI Target Peripheral for LatticeMico32 embedded microprocessor
Expanded ispLeverDSP support
Numerous updates to the Project Navigator
Updated 3rd party synthesis/simulation tools
Updated documentation navigation and new reference booksLatticeMico32 System
6.1 (plus SP1-2)
(Oct 2006 - Jan 2007)
New Device Support
LatticeECP2M
LatticeSC/M
Software Features
LatticeMico32 System
HDL Explorer
Memory Generation Tool for .mem file generation
Back-annotating assignments feature
New processes in Project Navigator
Undo last delete or unroute EPIC Device Editor
Expanded ispLeverDSP support
Numerous new IP cores available in IPexpress interface
Greater floorplanning capability in the pre-map stage of Design Planner
Enhanced spreadsheet and package view
Numerous updates and expanded device support in Schematic Editor
Updated FPGA design documentation
Updated 3rd party synthesis/simulation tools
6.0 Service Pack 1
(July 2006)
Additional New Device Support
LatticeECP2-12 (preliminary)
Software Enhancements
Dozens of enhancements to the ispLEVER tool set
Significantly improved accuracy of Power Calculator tool
Synplify for Lattice 8.6A Synthesis Update
Precision RTL 2005a Update 2 Synthesis Update
6.0
(May 2006)
New Device Support
LatticeECP2-50 (preliminary)
LatticeSC and LatticeSCM (contact your local Lattice sales office for more information)
MachXO (full production support)
LatticeXP (full production support)
Software Features
Design Planner tool integrates Preference Editor and Floorplanner
Schematic design library for Lattice FPGAs
FPGA Schematic and HDL Design tutorial
Expanded ispLeverDSP™ reference designs and blockset functions
Simulation resources for Cadence NC-Verilog, NC-VHDL, and Synopsys VCS
Expanded synthesis tool controls from within Project Navigator
TCL-format project file output for synthesis
Updated 3rd party synthesis/simulation tools
Intellectual Property
Connect to Lattice IP Server for the latest IP cores via IPexpress
Triple Speed Ethernet MAC
PCI
5.1 SP1-2
(January-March 2006)
New Device Support
LatticeXP: XP15, XP20 (preliminary)
MachXO: XO1200, XO2280 (preliminary)
Software Features
Improved performance: resource usage down 35%, performance up 25%.
Improved preference flow for better persistence
Comma Separated Value (.CSV) pin report for PCB interfaces
Automated timing preferences
Web-enabled Project Navigator news panel
Timing-driven Design Mapper
Multi-device device debug with ispTRACY Logic Analyzer
Device programming with ispVM: Flash Mode Turbo Algorithm
Updated Synthesis tools
Additional Power Calculator factors: VCCJ and VCCIO
Intellectual Property
Improved IP Delivery and Evaluation with New IPexpress Tool