Simulation and Analysis

ispLEVER includes a number of tools to help you simulate, analyze and optimize your design at multiple stages in the design process.

Active-HDL from Aldec Active-HDL Lattice Edition is included with ispLEVER for Windows, as well as for ispLEVER Classic and PAC-Designer. This fast, comprehensive and feature-rich simulation environment includes a number of powerful tools and features. Active HDL Version   Lattice Edition (ispLEVER, ispLEVER Classic and PAC-Designer) Project Management Single Design Support Design Flow Manager for Lattice Devices Workspace and Design Archiving Design Entry HDL and Text Editor Language Assistant with Templates and Auto-Complete Hierarchy Viewer with Configurations Support Macro, Tcl/Tk, Perl script support Lattice Libraries ispLEVER   Code Generation Tools Testbench Generation from Waveforms  Simulation and Verification VHDL IEEE 1987, 1993, 2002   Verilog HDL IEEE 1995, 2001 and 2005   SystemVerilog IEEE 1800 (Design)   Single Language Support   Mixed-Language Support (VHDL and Verilog or SystemVerilog and Verilog)   Simulate Encrypted IP (VHDL and Verilog)   Value Change Dump (VCD and Extended VCD) Support   Batch Mode Simulation/Regression Debug and Analysis Code Execution Tracing   Advanced Breakpoint Management   Standard Waveform Editor and List Viewer (AWF)   Memory Viewer Note 1: HDL line limit of 30K watermarked and 5K non-watermarked RTL lines, or 2000 watermarked and 500 non-watermarked instances. "Watermarked" items are pre-compiled Lattice design content. SSO Analyzer Simultaneous Switching Output (SSO) describes the noise caused by a large number of output drivers switching at the same time. Lattice has invented a new tool, the SSO Analyzer, which enables FPGA designers to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. Results are presented in a navigable HTML report and annotated onto the graphical Package View of the Design Planner tool. Power Calculator The ispLEVER Power Calculator includes an environment-aware power model, graphical power displays and a variety of useful reports. Thermal resistance options model real world thermal conditions, including heatsinks, airflow, and the printed circuit board complexity, while graphical power curves illustrate operating temperature profiles. Performance Analyst The Performance Analyst is a static timing analysis tool generates graphical spreadsheet-based reports containing worst-case signal delays. It allows you to filter this data to verify the speed of critical paths and identify performance bottlenecks. Lattice Logic Simulator The Lattice Logic Simulator supports the functional and timing simulation for CPLD and Power Manager II designs. Results are displayed in a straightforward waveform view. The Lattice Logic Simulator operates in both stand-alone and integrated environments.

ispLEVER Project Management   Design Entry HDL Synthesis ispLEVER Advanced Implementation Tools ispLEVER Simulation and Analysis   ispLEVER Device Programming ispLEVER In-system Logic Analysis