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ispLEVER includes a number of tools to help you simulate, analyze and optimize your design at multiple stages in the design process.
Active-HDL from Aldec
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 Active-HDL Lattice Edition is included with ispLEVER and ispLEVER PRO for Windows. Active-HDL Lattice Web Edition is an optional download module provided for ispLEVER Starter and Classic and PAC-Designer. This fast, comprehensive and feature-rich simulation environment includes a number of powerful tools and features. A comparison of the two versions is listed in the table below.
Active HDL Versions
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Lattice Edition
(ispLEVER and ispLEVER PRO) |
Lattice Web Edition
(ispLEVER Starter and Classic, and PAC-Designer) |
| Project Management |
| Single Design Support |
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| Design Flow Manager for Lattice Devices |
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| Workspace and Design Archiving |
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| Design Entry |
| HDL and Text Editor |
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| Language Assistant with Templates and Auto-Complete |
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| Hierarchy Viewer with Configurations Support |
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| Macro, Tcl/Tk, Perl script support |
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| Lattice Libraries |
ispLEVER
ispLEVER PRO |
ispLEVER Starter
ispLEVER Classic
PAC-Designer |
| Code Generation Tools |
| Testbench Generation from Waveforms |
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| Simulation and Verification |
| VHDL IEEE 1987, 1993, 2002 |
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Note 1 |
| Verilog HDL IEEE 1995, 2001 and 2005 |
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Note 1 |
| SystemVerilog IEEE 1800 (Design) |
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| Single Language Support |
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| Mixed-Language Support (VHDL and Verilog or SystemVerilog and Verilog) |
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| Simulate Encrypted IP (VHDL and Verilog) |
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| Value Change Dump (VCD and Extended VCD) Support |
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| Batch Mode Simulation/Regression |
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| Debug and Analysis |
| Code Execution Tracing |
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| Advanced Breakpoint Management |
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| Standard Waveform Editor and List Viewer (AWF) |
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| Memory Viewer |
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Note 1: HDL line limit of 30K watermarked and 5K non-watermarked RTL lines, or 2000 watermarked and 500 non-watermarked instances. "Watermarked" items are pre-compiled Lattice design content.
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SSO Analyzer
 Simultaneous Switching Output (SSO) describes the noise caused by a large number of output drivers switching at the same time. Lattice has invented a new tool, the SSO Analyzer, which enables FPGA designers to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. Results are presented in a navigable HTML report and annotated onto the graphical Package View of the Design Planner tool. |
Power Calculator
 The ispLEVER Power Calculator includes an environment-aware power model, graphical power displays and a variety of useful reports. Thermal resistance options model real world thermal conditions, including heatsinks, airflow, and the printed circuit board complexity, while graphical power curves illustrate operating temperature profiles. |
Performance Analyst
 The Performance Analyst is a static timing analysis tool generates graphical spreadsheet-based reports containing worst-case signal delays. It allows you to filter this data to verify the speed of critical paths and identify performance bottlenecks. |
Lattice Logic Simulator
 The Lattice Logic Simulator supports the functional and timing simulation for CPLD and Power Manager II designs. Results are displayed in a straightforward waveform view. The Lattice Logic Simulator operates in both stand-alone and integrated environments. |
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