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Included with ispLEVER, Reveal allow you to perform real-time logic analysis of internal device operation on a physical device in a system board.
Reveal Logic Analyzer
 Reveal is the next-generation in-system logic analysis tool included with ispLEVER. Reveal uses a signal-centric model for embedded logic debug; the user first defines signals of interest with the Reveal Inserter, which adds the instrumentation along with the proper connections to enable the required observations. In-system analysis can then be performed with the Reveal Logic Analyzer (shown in the screen shot). The ability to specify complex, multi-event triggering sequences makes system-level design debug smoother and faster. |
ispTRACY Logic Analyzer (Replaced by Reveal)
 With ispTRACY, small user-defined IP modules can be used to feed live signal information from internal nodes (i.e. signals not accessible at device pins) of one or more FPGAs back to the PC. This information can then be displayed and manipulated with the ispTRACY Logic Analyzer interface. This efficient tool cuts development time by helping you de-bug your design in ways that are impossible with more traditional hardware methods. |
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