In-system Logic Analysis

Reveal is the next-generation in-system logic analysis tool included with ispLEVER. Reveal uses a signal-centric model for embedded logic debug; the user first defines signals of interest with the Reveal Inserter, which adds the instrumentation along with the proper connections to enable the required observations. In-system analysis can then be performed with the Reveal Logic Analyzer (shown in the screen shot). The ability to specify complex, multi-event triggering sequences makes system-level design debug smoother and faster.