ispLEVER is the previous generation design environment for Lattice FPGA products. It includes a comprehensive set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis, and more.
ispLEVER is provided for Windows or Linux platforms. ispLEVER is supported for existing customers. New customers should purchase Lattice Diamond which can be ordered from your local sales representative or purchased online.
ispLEVER and Lattice Diamond also includes industry leading 3rd party tools from Lattice partners Synopsys® (synthesis) and Aldec® (simulation).
ispLEVER 8.2 is now made available to existing ispLEVER users. New customers should use Lattice Diamond.
ispLEVER for Windows and Linux features the industry-leading Synplify Pro® VHDL and Verilog synthesis tool from Synposys, including tools like HDL Analyst for powerful Verilog and VHDL view/debug.
ispLEVER for Windows also includes the very high performance Aldec Active-HDL Lattice Edition timing and functional simulator, which yields fast simulation results and includes mixed language support.
Windows: 2000 / XP / Vista (32-bit)
Linux: Red Hat Enterprise v3, v4, and v5; Novell SUSE Enterprise v10
Lattice Programmable logic families except MachXO2
Click here to see what's new in ispLEVER 8.2.
Project Navigator is the ispLEVER project management interface. The entire set of ispLEVER tools can be accessed from this interface. Your project files, including the current target device, are shown in hierarchical format on the left side of the screen. Tasks associated with those project files are shown on the right side of the screen. Other optional windows display revision control information, and a log file. Completing your design can be as simple as double-clicking the task you want to perform, and letting ispLEVER do the rest.
The Block Modular Design (BMD) flow for FPGA design allows large FPGA designs to be partitioned into more manageable blocks; which independent teams can then develop in parallel. The blocks can then be re-integrated for the final design - retaining the place and route definitions and timing characteristics of the individual blocks. BMD-related features are compatible with LatticeEC, LatticeECP and LatticeXP FPGAs, as well as the MachXO devices.
ispLEVER includes a built-in Revision Control System to help you try different settings in your design without losing your previous design states. Switching from one revision to the next takes only one click. Revisions can be renamed to your preference. The revision control system can also be turned-off if you don't want to use it.
ispLEVER helps you complete your HDL or schematic design work with simple and powerful tools. Whether your design includes files in multiple locations, generated from multiple sources, or of multiple formats, ispLEVER helps you get everything working together.
IPexpress is the interface to the Lattice catalog of functional modules, reference designs, and intellectual property(IP), all optimized for Lattice programmable products. IPexpress helps accellerate the design process by helping you smoothly configura and integrate these functions into your custom design. Lattice IP cores include some of the most popular industry-standard functions such as PCI bus controllers, DDR memory controllers, Ethernet MACs, DSP functions and many more. To learn more about these IP cores, click here.
ispLEVER includes an intuitive HDL text editor that includes keyword highlight support for: VHDL, Verilog HDL, EDIF, and the Lattice Preference Language. You also set your favorite editor as the default.
Lastly, ispLEVER includes dozens of DSP-function blocks optimized for use in Lattice programmable technologies. These blocks are for use in the MATLAB/Simulink DSP design environment (Available separately from The MathWorks). For more information on The MathWorks products visit their website.
Lattice is committed to providing the industry's best HDL synthesis tools as standard features of the ispLEVER flow. We work closely with leading synthesis developers to continuously optimize design utilization and improve the quality of results, so you can be sure to realize the maximum potential of Lattice programmable products.
Synplify Pro for Lattice synthesis is a high-performance, sophisticated logic synthesis engine that delivers fast, highly efficient FPGA designs. The simple user interface and powerful synthesis engine combine to deliver optimal results quickly.
Synplify Pro for Lattice is included with ispLEVER and ispLEVER Classic.
ABEL-HDL is a hierarchical logic description language to to describe digital designs with equations, truth tables, state diagrams, or any combination of the three. The ABEL-HDL Compiler will optimize design logic and produce BLIF format output for Lattice device fitters. ABEL-HDL is ideal designers new to programmable logic design. The ispLEVER ABEL-HDL Compiler supports the following device families: ispMACH 4000Z, ispMACH4000V/B/C, ispMACH 4A5, ispGAL, and GAL.
ispLEVER includes a full suite of tools that give you as much control over the implementation of your design as you want or need. All of these tools are optional. If you prefer, you can let ispLEVER determine optimal placement and routing. But, if you have special requirements or need detailed control over your design implementation, ispLEVER has the advanced tools you need.
The ispLEVER Design Planner helps you manage all aspects of design implementation. From the Design Planner, you can launch tools that give you detailed control over various aspects of your design implementation. These tools are described in more detail below.
The ispLEVER Design Planner includes a flexible interface (Spreadsheet view) to help you define timing constraints (frequency/period, I/O timing), assign I/O types, set global attributes, define PLL specifications, and more. All design preferences are stored in a centralized database file, which can be accessed and changed from any point in the design process.
Also accessible via the ispLEVER Design Planner, Package View helps you perform tasks such as drag and drop I/O assignments, identify specific I/Os, and visually picture how the pins on the device are defined. Pin assignment information can be exported to .csv reports for use in other applications.
The ispLEVER Design Planner also includes pre- or post- PAR Floorplanning tools. From a single control window, a number of cross-functional tools can be launched to help you assign design elements to groups and/or regions, physically map and manipulate device resources with a visual interface, and run detailed timing analysis reports. Changes in one of these tools are reflected in the others, giving you multiple entry paths into your design.
The EPIC Device Editor provides intimate access to the physical implementation of your design. Physical details like route interconnect, physical element programming, and I/O buffer configuration can be examined or directly edited after the PAR process, giving you ultimate control.
ispLEVER includes a number of tools to help you simulate, analyze and optimize your design at multiple stages in the design process.
Active-HDL Lattice Edition is included with ispLEVER for Windows, as well as for ispLEVER Classic and PAC-Designer. This fast, comprehensive and feature-rich simulation environment includes a number of powerful tools and features.
Simultaneous Switching Output (SSO) describes the noise caused by a large number of output drivers switching at the same time. Lattice has invented a new tool, the SSO Analyzer, which enables FPGA designers to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. Results are presented in a navigable HTML report and annotated onto the graphical Package View of the Design Planner tool.
The ispLEVER Power Calculator includes an environment-aware power model, graphical power displays and a variety of useful reports. Thermal resistance options model real world thermal conditions, including heatsinks, airflow, and the printed circuit board complexity, while graphical power curves illustrate operating temperature profiles.
The Performance Analyst is a static timing analysis tool generates graphical spreadsheet-based reports containing worst-case signal delays. It allows you to filter this data to verify the speed of critical paths and identify performance bottlenecks.
Included with ispLEVER, Reveal allows you to perform real-time logic analysis of internal device operation on a physical device in a system board.
Reveal is the next-generation in-system logic analysis tool included with ispLEVER. Reveal uses a signal-centric model for embedded logic debug; the user first defines signals of interest with the Reveal Inserter, which adds the instrumentation along with the proper connections to enable the required observations. In-system analysis can then be performed with the Reveal Logic Analyzer (shown in the screen shot). The ability to specify complex, multi-event triggering sequences makes system-level design debug smoother and faster.