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 Lattice is committed to providing the industry's best HDL synthesis tools as standard features of the ispLEVER flow. We work closely with leading synthesis developers to continuously optimize design utilization and improve the quality of results, so you can be sure to realize the maximum potential of Lattice programmable products.
Click the items below to learn more about Synthesis tools included with ispLEVER.
Synplify Pro for Lattice - Synthesis from Synplicity
 Synplify Pro for Lattice synthesis is a high-performance, sophisticated logic synthesis engine that utilizes proprietary Behavior Extracting Synthesis Technology (B.E.S.T.") to deliver fast, highly efficient FPGA and CPLD designs. The simple user interface and powerful synthesis engine combine to deliver optimal results quickly.
Synplify Pro also includes advanced tools and features like HDL Analyst, Mixed VHDL/Verilog support, automatic re-timing and more. |
ABEL-HDL Compiler for CPLDs and SPLDs
| ABEL-HDL is a hierarchical logic description language to to describe digital designs with equations, truth tables, state diagrams, or any combination of the three. The ABEL-HDL Compiler will optimize design logic and produce BLIF format output for Lattice device fitters. ABEL-HDL is ideal designers new to programmable logic design. The ispLEVER ABEL-HDL Compiler supports the following device families: ispMACH 4000Z, ispMACH4000V/B/C, ispMACH 4A5, ispGAL, and GAL. |
Device Libraries
| ispLEVER includes device libraries for those who already have alternate versions of the above synthesis tools for any operating system. |
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