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 Lattice is committed to providing the industry's best HDL synthesis tools as standard features of the ispLEVER flow. We work closely with leading synthesis developers to continuously optimize design utilization and improve the quality of results, so you can be sure to realize the maximum potential of Lattice programmable products.
Click the items below to learn more about Synthesis tools included with ispLEVER.
Synplify Pro for Lattice - Synthesis from Synplicity
 Synplify Pro for Lattice synthesis is a high-performance, sophisticated logic synthesis engine that delivers fast, highly efficient FPGA designs. The simple user interface and powerful synthesis engine combine to deliver optimal results quickly.
Synplify Pro for Lattice is included with ispLEVER and ispLEVER PRO. Synplify for Lattice is included with ispLEVER Starter and Classic. The table below describes the differences between these two tools.
HDL Synthesis Tools
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Synplify Pro for Lattice
(ispLEVER and ispLEVER PRO) |
Synplify for Lattice
(ispLEVER Starter and Classic) |
| Behavior Extracting Synthesis Technology (BEST) produces globally optimized designs in a fraction of the time required for traditional tools |
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| Comprehensive Language Compiler for supporting a wide range of Verilog and VHDL language constructs |
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| SCOPE constraints editor for spreadsheet-like entry of design constraints for synthesis, place and route |
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| Integrated module generation for high-performing, area-efficient implementation of arithmetic/datapath functions |
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| Automatic RAM inferencing for technology independent RTL source code |
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| Integrated language-sensitive HDL source code editor with syntax checker |
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| Automatic register balancing of pipelined multipliers and ROMs for improved performance |
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| Customized mapping software for each FPGA device family ensures optimal implementation in the target device and technology independence |
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| HDL Analyst automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code |
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| Mixed Verilog and VHDL support |
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| Automatic re-timing (balancing registers across combinatorial logic) for improved performance |
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| Automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA |
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ABEL-HDL Compiler for CPLDs and SPLDs
| ABEL-HDL is a hierarchical logic description language to to describe digital designs with equations, truth tables, state diagrams, or any combination of the three. The ABEL-HDL Compiler will optimize design logic and produce BLIF format output for Lattice device fitters. ABEL-HDL is ideal designers new to programmable logic design. The ispLEVER ABEL-HDL Compiler supports the following device families: ispMACH 4000Z, ispMACH4000V/B/C, ispMACH 4A5, ispGAL, and GAL. |
Device Libraries
| ispLEVER includes device libraries for those who already have alternate versions of the above synthesis tools for any operating system. |
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